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Factor out write_pirq_routing_table() for all GeodeLX targets.

Browse source 
Compile tested on norwich, alix1c and dbe62. msm800sev is not affected
and dbe61 is broken anyway.

svn is unable to create a valid patch for what I did, so I'll have to
commit this myself. To reproduce, perform the following commands, then
apply the patch:

svn mv mainboard/amd/norwich/irq_tables.c mainboard/amd/norwich/irq_tables.h
svn mv mainboard/pcengines/alix1c/irq_tables.c mainboard/pcengines/alix1c/irq_tables.h
svn mv mainboard/artecgroup/dbe61/irq_tables.c mainboard/artecgroup/dbe61/irq_tables.h
svn mv mainboard/artecgroup/dbe62/irq_tables.c mainboard/artecgroup/dbe62/irq_tables.h

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

tested on alix1c. Boots, USB, graphics, and ethernet all work.

Acked-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@628 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-03-01 21:33:51 +00:00
parent c10ac2884b
commit 9c2060a5e5
9 changed files with 8 additions and 152 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
Makefile
View file

@ -85,6 +85,7 @@ export MAINBOARDDIR
COREBOOTINCLUDE := -I$(src) -Iinclude \
-I$(src)/include \
-I$(src)/include/arch/$(ARCH)/ \
-I$(src)/mainboard/$(MAINBOARDDIR)/ \
-include $(obj)/config.h \
-include $(obj)/build.h

2
mainboard/amd/norwich/Makefile
View file

@ -26,7 +26,7 @@ INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/southbridge/amd/cs5536/smbus_initram.c \
$(src)/arch/x86/geodelx/geodelx.c
STAGE2_MAINBOARD_OBJ = irq_tables.o
STAGE2_MAINBOARD_OBJ =
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"

46
mainboard/amd/norwich/irq_tables.c → mainboard/amd/norwich/irq_tables.h
View file

@ -93,49 +93,3 @@ const struct irq_routing_table intel_irq_routing_table = {
{0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
int i, j, k, num_entries;
unsigned char pirq[4];
u16 chipset_irq_map;
u32 pciAddr, pirtable_end;
struct irq_routing_table *pirq_tbl;
pirtable_end = copy_pirq_routing_table(addr);
/* Set up chipset IRQ steering. */
pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
chipset_irq_map);
outl(pciAddr & ~3, 0xCF8);
outl(chipset_irq_map, 0xCFC);
pirq_tbl = (struct irq_routing_table *) (addr);
num_entries = (pirq_tbl->size - 32) / 16;
/* Set PCI IRQs. */
for (i = 0; i < num_entries; i++) {
printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
for (j = 0; j < 4; j++) {
printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,
pirq_tbl->slots[i].irq[j].bitmap);
/* Finds lsb in bitmap to IRQ#. */
for (k = 0;
(!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))
&& (pirq_tbl->slots[i].irq[j].bitmap != 0);
k++);
pirq[j] = k;
printk(BIOS_DEBUG, "PIRQ: %d\n", k);
}
/* Bus, device, slots IRQs for {A,B,C,D}. */
pci_assign_irqs(pirq_tbl->slots[i].bus,
pirq_tbl->slots[i].devfn >> 3, pirq);
}
/* Put the PIR table in memory and checksum. */
return pirtable_end;
}

0
mainboard/artecgroup/dbe61/irq_tables.c → mainboard/artecgroup/dbe61/irq_tables.h
View file

2
mainboard/artecgroup/dbe62/Makefile
View file

@ -25,7 +25,7 @@ INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \
$(src)/arch/x86/geodelx/geodelx.c
STAGE2_MAINBOARD_OBJ = irq_tables.o
STAGE2_MAINBOARD_OBJ =
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"

46
mainboard/artecgroup/dbe62/irq_tables.c → mainboard/artecgroup/dbe62/irq_tables.h
View file

@ -68,49 +68,3 @@ const struct irq_routing_table intel_irq_routing_table = {
{0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
int i, j, k, num_entries;
unsigned char pirq[4];
u16 chipset_irq_map;
u32 pciAddr, pirtable_end;
struct irq_routing_table *pirq_tbl;
pirtable_end = copy_pirq_routing_table(addr);
/* Set up chipset IRQ steering. */
pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
chipset_irq_map);
outl(pciAddr & ~3, 0xCF8);
outl(chipset_irq_map, 0xCFC);
pirq_tbl = (struct irq_routing_table *) (addr);
num_entries = (pirq_tbl->size - 32) / 16;
/* Set PCI IRQs. */
for (i = 0; i < num_entries; i++) {
printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
for (j = 0; j < 4; j++) {
printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,
pirq_tbl->slots[i].irq[j].bitmap);
/* Finds lsb in bitmap to IRQ#. */
for (k = 0;
(!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))
&& (pirq_tbl->slots[i].irq[j].bitmap != 0);
k++);
pirq[j] = k;
printk(BIOS_DEBUG, "PIRQ: %d\n", k);
}
/* Bus, device, slots IRQs for {A,B,C,D}. */
pci_assign_irqs(pirq_tbl->slots[i].bus,
pirq_tbl->slots[i].devfn >> 3, pirq);
}
/* Put the PIR table in memory and checksum. */
return pirtable_end;
}

2
mainboard/pcengines/alix1c/Makefile
View file

@ -25,7 +25,7 @@ INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \
$(src)/arch/x86/geodelx/geodelx.c
STAGE2_MAINBOARD_OBJ = irq_tables.o
STAGE2_MAINBOARD_OBJ =
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"

57
mainboard/pcengines/alix1c/irq_tables.c → mainboard/pcengines/alix1c/irq_tables.h
View file

@ -17,18 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <lib.h>
#include <console.h>
#include <device/device.h>
#include <device/pci.h>
#include <string.h>
#include <msr.h>
#include <io.h>
#include <pirq_routing.h>
#include <amd_geodelx.h>
#include "../../../southbridge/amd/cs5536/cs5536.h"
/* Platform IRQs */
@ -112,49 +101,3 @@ const struct irq_routing_table intel_irq_routing_table = {
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
int i, j, k, num_entries;
unsigned char pirq[4];
u16 chipset_irq_map;
u32 pciAddr, pirtable_end;
struct irq_routing_table *pirq_tbl;
pirtable_end = copy_pirq_routing_table(addr);
/* Set up chipset IRQ steering. */
pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
chipset_irq_map);
outl(pciAddr & ~3, 0xCF8);
outl(chipset_irq_map, 0xCFC);
pirq_tbl = (struct irq_routing_table *) (addr);
num_entries = (pirq_tbl->size - 32) / 16;
/* Set PCI IRQs. */
for (i = 0; i < num_entries; i++) {
printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
for (j = 0; j < 4; j++) {
printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,
pirq_tbl->slots[i].irq[j].bitmap);
/* Finds lsb in bitmap to IRQ#. */
for (k = 0;
(!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))
&& (pirq_tbl->slots[i].irq[j].bitmap != 0);
k++);
pirq[j] = k;
printk(BIOS_DEBUG, "PIRQ: %d\n", k);
}
/* Bus, device, slots IRQs for {A,B,C,D}. */
pci_assign_irqs(pirq_tbl->slots[i].bus,
pirq_tbl->slots[i].devfn >> 3, pirq);
}
/* Put the PIR table in memory and checksum. */
return pirtable_end;
}

4
southbridge/amd/cs5536/Makefile
View file

@ -23,6 +23,10 @@ ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)
STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o
ifeq ($(CONFIG_PIRQ_TABLE),y)
STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/irq_tables.o
endif
STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o
endif