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https://github.com/fail0verflow/switch-coreboot.git
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9c2060a5e5
Compile tested on norwich, alix1c and dbe62. msm800sev is not affected and dbe61 is broken anyway. svn is unable to create a valid patch for what I did, so I'll have to commit this myself. To reproduce, perform the following commands, then apply the patch: svn mv mainboard/amd/norwich/irq_tables.c mainboard/amd/norwich/irq_tables.h svn mv mainboard/pcengines/alix1c/irq_tables.c mainboard/pcengines/alix1c/irq_tables.h svn mv mainboard/artecgroup/dbe61/irq_tables.c mainboard/artecgroup/dbe61/irq_tables.h svn mv mainboard/artecgroup/dbe62/irq_tables.c mainboard/artecgroup/dbe62/irq_tables.h Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> tested on alix1c. Boots, USB, graphics, and ethernet all work. Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@628 f3766cd6-281f-0410-b1cd-43a5c92072e9
95 lines
4 KiB
C
95 lines
4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <string.h>
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#include <msr.h>
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#include <io.h>
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#include <pirq_routing.h>
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#include <amd_geodelx.h>
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#include "../../../southbridge/amd/cs5536/cs5536.h"
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/* Number of slots and devices in the PIR table */
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#define SLOT_COUNT 6
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/* Platform IRQs */
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#define PIRQA 11
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#define PIRQB 10
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#define PIRQC 11
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#define PIRQD 10
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/* Map */
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#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
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#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
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#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
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#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
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/* Link */
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#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
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#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
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#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
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#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
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/*
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* Norwich interrupt wiring.
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*
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* Devices are:
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*
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* 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31)
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* 00:01.1 Graphics device: Advanced Micro Devices [AMD] Geode LX Graphics
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* 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
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* 00:0b.0 slot3
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* 00:0c.0 slot4
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* 00:0d.0 slot1
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* 00:0e.0 slot2
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* 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)
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* 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01)
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* 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01)
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* 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02)
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* 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
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*
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*/
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE,
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PIRQ_VERSION,
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32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */
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0x00, /* Where the interrupt router lies (bus) */
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(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
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0x00, /* IRQs devoted exclusively to PCI usage */
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0x100B, /* Vendor */
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0x002B, /* Device */
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0, /* Crap (miniport) */
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
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0x00, /* Checksum */
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{
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/* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
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{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
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{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */
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{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */
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{0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */
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{0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */
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}
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};
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