mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
9c2060a5e5
Compile tested on norwich, alix1c and dbe62. msm800sev is not affected and dbe61 is broken anyway. svn is unable to create a valid patch for what I did, so I'll have to commit this myself. To reproduce, perform the following commands, then apply the patch: svn mv mainboard/amd/norwich/irq_tables.c mainboard/amd/norwich/irq_tables.h svn mv mainboard/pcengines/alix1c/irq_tables.c mainboard/pcengines/alix1c/irq_tables.h svn mv mainboard/artecgroup/dbe61/irq_tables.c mainboard/artecgroup/dbe61/irq_tables.h svn mv mainboard/artecgroup/dbe62/irq_tables.c mainboard/artecgroup/dbe62/irq_tables.h Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> tested on alix1c. Boots, USB, graphics, and ethernet all work. Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@628 f3766cd6-281f-0410-b1cd-43a5c92072e9
32 lines
1.1 KiB
Makefile
32 lines
1.1 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 coresystems GmbH
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## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)
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STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o
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ifeq ($(CONFIG_PIRQ_TABLE),y)
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STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/irq_tables.o
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endif
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STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o
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endif
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