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SAROO/FPGA
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tpu d12cadbbc1 FPGA bugfix 
MCU bugfix
2023-11-11 12:59:22 +08:00
..
.gitignore Update HW to v13(bugfix) 2023-06-06 11:20:02 +08:00
cacheblk.v Update HW to v13(bugfix) 2023-06-06 11:20:02 +08:00
cachebus.v Update HW to v13(bugfix) 2023-06-06 11:20:02 +08:00
cdcfifo.qip Update HW to v13(bugfix) 2023-06-06 11:20:02 +08:00
cdcfifo.v Update HW to v13(bugfix) 2023-06-06 11:20:02 +08:00
mainpll.ppf Update HW to v13(bugfix) 2023-06-06 11:20:02 +08:00
mainpll.qip Update HW to v13(bugfix) 2023-06-06 11:20:02 +08:00
mainpll.v Update HW to v13(bugfix) 2023-06-06 11:20:02 +08:00
make_jic.tcl Update HW to v13(bugfix) 2023-06-06 11:20:02 +08:00
memhub.v FPGA bugfix 2023-11-11 12:59:22 +08:00
readme.txt Update HW to v13(bugfix) 2023-06-06 11:20:02 +08:00
ssmaster.cdf Update HW to v13(bugfix) 2023-06-06 11:20:02 +08:00
ssmaster.cof Update HW to v13(bugfix) 2023-06-06 11:20:02 +08:00
SSMaster.qpf Update HW to v13(bugfix) 2023-06-06 11:20:02 +08:00
SSMaster.qsf Update HW to v13(bugfix) 2023-06-06 11:20:02 +08:00
SSMaster.sdc Update HW to v13(bugfix) 2023-06-06 11:20:02 +08:00
SSMaster.v FPGA bugfix 2023-11-11 12:59:22 +08:00
tsdram.v FPGA bugfix 2023-11-11 12:59:22 +08:00

readme.txt

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V12相对于V11的改动:

1: 移除了qsys相关的组件。qsys自带的SDRAM控制器效率比较低，仅支持单次读写。
2: 实现了一个简单的SDRAM控制器，支持4次突发读。
3: 实现了一个双主端口的总线架构，每个主端口有8字节的cache。
4: 由于CDC缓存放在STM32端，现在由STM32负责填充CDC FIFO。