SAROO/FPGA/SSMaster.sdc
tpu d1abb17e53 Update HW to v13(bugfix)
Change directory structs
2023-06-06 11:20:02 +08:00

8 lines
248 B
Tcl

#**************************************************************
# Create Clock
#**************************************************************
derive_pll_clocks -create_base_clocks
create_clock -name {ST_ALE} -period 10.000 [get_ports {ST_ALE}]