mirror of
https://github.com/array-in-a-matrix/SAROO.git
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110 lines
2.5 KiB
Verilog
110 lines
2.5 KiB
Verilog
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///////////////////////////////////////////////////////
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// Module: Cache Block manager //
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///////////////////////////////////////////////////////
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module cacheblk(
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reset, clk,
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cache_addr, cache_data1d, cache_valid, data_valid, cdata,
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cache_update_a, umask_a, uaddr_a, udata_a,
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cache_update_b, umask_b, uaddr_b, udata_b,
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cache_invalid, iaddr
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);
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///////////////////////////////////////////////////////
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// Pins //
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///////////////////////////////////////////////////////
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// system
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input reset;
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input clk;
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// cache interface
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output[25:3] cache_addr;
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output[63:0] cache_data1d;
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output[ 3:0] cache_valid;
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input data_valid;
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input[15:0] cdata;
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// cache update
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input cache_update_a;
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input[ 1:0] umask_a;
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input[25:0] uaddr_a;
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input[15:0] udata_a;
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input cache_update_b;
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input[ 1:0] umask_b;
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input[25:0] uaddr_b;
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input[15:0] udata_b;
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// cache incalid
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input cache_invalid;
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input[25:0] iaddr;
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///////////////////////////////////////////////////////
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// cache block manager //
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///////////////////////////////////////////////////////
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reg[15:0] cache_data[3:0];
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reg[25:3] cache_addr;
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reg[ 3:0] cache_valid;
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reg[ 1:0] dcnt;
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assign cache_data1d = {cache_data[3],cache_data[2],cache_data[1],cache_data[0]};
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// cache_data
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always @(posedge clk)
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begin
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if(cache_update_a && uaddr_a[25:3]==cache_addr) begin
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if(umask_a[1]==0) cache_data[uaddr_a[2:1]][15:8] <= udata_a[15:8];
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if(umask_a[0]==0) cache_data[uaddr_a[2:1]][ 7:0] <= udata_a[ 7:0];
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end else if(cache_update_b && uaddr_b[25:3]==cache_addr) begin
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if(umask_b[1]==0) cache_data[uaddr_b[2:1]][15:8] <= udata_b[15:8];
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if(umask_b[0]==0) cache_data[uaddr_b[2:1]][ 7:0] <= udata_b[ 7:0];
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end else if(data_valid) begin
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// 是否已经被cache_update填充?
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if(cache_valid[dcnt]==0) begin
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cache_data[dcnt] <= cdata;
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end
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end
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end
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// cache_addr
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always @(negedge reset or posedge clk)
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begin
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if(reset==0) begin
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cache_addr <= 23'h555555;
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end else if(cache_invalid)begin
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cache_addr <= iaddr[25:3];
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end
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end
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// cache_valid
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always @(negedge reset or posedge clk)
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begin
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if(reset==0) begin
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cache_valid <= 0;
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end else if(cache_invalid)begin
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cache_valid <= 0;
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end else if(data_valid) begin
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cache_valid[dcnt] <= 1'b1;
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end
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end
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// dcnt
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always @(negedge reset or posedge clk)
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begin
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if(reset==0) begin
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dcnt <= 0;
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end else if(cache_invalid)begin
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dcnt <= 0;
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end else if(data_valid) begin
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dcnt <= dcnt+1'b1;
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end
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end
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endmodule
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