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Docs: New TODO moved to EMU, old renamed to old_todo Docs: Old coding style is deprecated (old_style.txt) Docs: Removed mention about CubeDocumented and fixed old emails RE: boot.s, proved first asm line (lis instruction parameter) RE: Added PAL and NTSC Boot and IPL IDA files RE: Some work on NTSC IPL (identified many lib calls, including OS, GX) RE: Added EXI Bootrom descrambler by segher RE: GXInit RE: Internal GX lib structures (GXPrivate.h) RE: More details on lomem (OS versions) RE: OSInit and OS.c RE: OSAlloc (heap allocator) RE: Very first code of Metrowerk runtime (__start.c) Docs: Added copy of http://gcdev.narod.ru Source\Utils: Command processor (Cmd.c) Source\Utils: File wrapper Source\Utils: Gekko disasm cleaned up and ported to plain C Source\Utils: Double-linked lists Source\Utils: Ported old Profiler code Source\Utils: String utils
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<center><u><h2>GAMECUBE Video Interface</h2></u></center>
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<BR><b>Vertical Timing Register</b> (R/W) [16] <b><font face=Verdana color=PURPLE size=2pt>CC002000</font></b><BR><BR>This register setups the
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vertical timing. The value ACV is double buffered <PRE> EQU 3:0 Equalization pulse in half lines. -
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ACV 13:4 Active video in full lines. -
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</PRE><BR><b>Display Configuration Register</b> (R/W) [16] <b><font face=Verdana color=PURPLE size=2pt>CC002002</font></b><BR><BR>This register set ups and enables VI. Generally, VI
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should be reset before enabling it. This resets the states into some known
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values. <PRE> ENB 0 This bit enables the video timing generation and data request. 0
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RST 1 This bit clears all data request and puts VI into its idle state. 0
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NIN 2 To select interlace or non-interlace mode. NIN = 0: interlace, 0
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NIN = 1: non-interlace. In non-interlace mode, the top field is
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drawn at field rate while the bottom field is not displayed.
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DLR 3 This bit selects the 3D display mode.
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LE0 5:4 Gun trigger mode. It enables the Display Latch Register 0. When 0
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the mode is 1 or 2, it will clear itself(off) automatically when a
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gun trigger is detected or at time out. This field is double buffered.
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0 off
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1 on for 1 field
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2 on for 2 fields
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3 always on
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LE1 7:6 To enable Display Latch Register 1. See the description of LE0. 0
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FMT 9:8 Indicates current video format: 0
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0 NTSC
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1 PAL
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2 MPAL
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3 Debug (CCIR656)
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</PRE><BR><b>Horizontal Timing 0 Register</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC002004</font></b><BR><BR>This register setups
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the horizontal timing. <PRE> HLW 9:0 Half line width. -
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HCE 22:16 Horizontal sync start to color burst end. -
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HCS 30:24 Horizontal sync start to color burst start. -
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</PRE><BR><b>Horizontal Timing 1 Register</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC002008</font></b><BR><BR>This register setups
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the horizontal timing. <PRE> HSY 6:0 Horizontal sync width. -
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HBE 16:7 Horizontal sync start to horizontal blanking end. -
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HBS 26:17 Half line to horizontal blanking start. -
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</PRE><BR><b>Odd Field Vertical Timing Register</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC00200C</font></b><BR><BR>This register
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sets up the pre-blanking and post-blanking intervals of odd fields. The values
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PRB and PSB are double buffered. <PRE> PRB 9:0 Pre-blanking in half lines. -
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PSB 25:16 Post-blanking in half lines. -
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</PRE><BR><b>Even Field Vertical Timing Register</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC002010</font></b><BR><BR>This register
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sets up the pre-blanking and post-blanking intervals of even fields. The values
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PRB and PSB are double buffered. <PRE> PRB 9:0 Pre-blanking in half lines. -
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PSB 25:16 Post-blanking in half lines. -
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</PRE><BR><b>Odd Field Burst Blanking Interval Register</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC002014</font></b><BR><BR>This
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register sets up the burst blanking interval of odd fields. <PRE> BS1 4:0 Field 1 start to burst blanking start in half lines. -
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BE1 15:5 Field 1 start to burst blanking end in half lines. -
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BS3 20:16 Field 3 start to burst blanking start in half lines. -
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BE3 31:21 Field 3 start to burst blanking end in half lines. -
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</PRE><BR><b>Even Field Burst Blanking Interval Register</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC002018</font></b><BR><BR>This
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register sets up the burst-blanking interval of even fields. <PRE> BS2 4:0 Field 2 start to burst blanking start in half lines. -
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BE2 15:5 Field 2 start to burst blanking end in half lines. -
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BS4 20:16 Field 4 start to burst blanking start in half lines. -
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BE4 31:21 Field 4 start to burst blanking end in half lines. -
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</PRE><BR><b>Top Field Base Register L</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC00201C</font></b><BR><BR>This register specifies
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the display origin of the top field of a picture in 2D display mode or for the
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left picture in 3D display mode. <PRE> FBB 23:0 External memory address of the frame buffer image. -
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XOF 27:24 Horizontal offset, in pixels, of the left-most pixel -
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within the first word of the fetched picture. -
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</PRE><BR><b>Top Field Base Register R</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC002020</font></b><BR><BR>This register specifies
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the base address of the top field for the right picture in the 3D display mode.
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It is not used in 2D display mode. <PRE> FBB 23:0 External memory address of the frame buffer image. -
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</PRE><BR><b>Bottom Field Base Register L</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC002024</font></b><BR><BR>This register specifies
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the display origin of the bottom field of a picture in 2D display mode or for
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the left picture in 3D display mode. <PRE> FBB 23:0 External memory address of the frame buffer image. -
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</PRE><BR><b>Bottom Field Base Register R</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC002028</font></b><BR><BR>This register specifies
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the base address of the bottom field for the right picture in the 3D display
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mode. It is not used in 2D display mode. <PRE> FBB 23:0 External memory address of the frame buffer image. -
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</PRE><BR><b>Picture Configuration Register</b> (R/W) <BR><BR>This register
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specifies the picture configuration. <PRE> STD 7:0 Stride per line in words. -
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WPL 14:8 Number of reads per line in words. -
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</PRE><BR><b>Display Position Register</b> (R) [32] <b><font face=Verdana color=PURPLE size=2pt>CC00202C</font></b><BR><BR>This register contains the
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current raster position. <BR><BR>The Horizontal Count is in pixels and runs from
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1 to # pixels per line. It is reset to 1 at the beginning of every line.
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<BR><BR>The Vertical Count is in lines (on a frame basis) and runs from 1 to #
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lines per frame. It is 1 at the beginning of pre-equalization. This is a frame
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line count. So for example: for NTSC vcount=264 is the first (full) line in the
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second field and vcount=525 is the last line in the frame (fields being numbered
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1-4). For non-interlaced modes vcount is on a field-by-field basis (for NTSC
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vcount ranges from 1-263). <BR><BR>This counting scheme applies the Display
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Position, Display Interrupt, and Display Latch registers. <PRE> HCT 10:0 Horizontal count. -
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VCT 26:16 Vertical count. -
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</PRE><BR><b>Display Interrupt Register 0</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC002030</font></b><BR><BR>There are a total of
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four display interrupt registers (0-3). They are used to generate interrupts to
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the main processor at different positions within a field. Each register has a
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separate enable bit. The interrupt is cleared by writing a zero to the status
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flag (INT). <PRE> HCT 10:0 Horizontal count to generate interrupt. -
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VCT 26:16 Vertical count to generate interrupt. -
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ENB 28 Interrupt is enabled if this bit is set. 0
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INT 31 Interrupt status. A "1" indicates that an interrupt 0
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is active.
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</PRE><BR><b>Display Interrupt Register 1</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC002034</font></b><BR><BR>See the description of
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Display Interrupt Register 0. <BR><BR><BR><b>Display Interrupt Register 2</b> (R/W)
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[32] <b><font face=Verdana color=PURPLE size=2pt>CC002038</font></b><BR><BR>See the description of Display Interrupt Register 0. <BR><BR><BR><b>Display
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Interrupt Register 3</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC00203C</font></b><BR><BR>See the description of Display Interrupt
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Register 0. <BR><BR><BR><b>Display Latch Register 0</b> (R/W) <BR><BR>The Display Latch
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Register 0 latches the value of the Display Position Register at the rising edge
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of the gt0 signal. The trigger flag is set if a gun trigger is detected. Writing
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a zero to the register clear the trigger flag. <PRE> HCT 10:0 Horizontal count. 0
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VCT 26:16 Vertical count. 0
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TRG 31 Trigger flag. 0
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</PRE><BR><b>Display Latch Register 1</b> (R/W) <BR><BR>See the description of
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Display Latch Register 0. This register is latched on the rising edge of the gt1
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signal. <BR><BR><BR><b>Output Polarity Register</b> (R/W) <BR><BR>This register sets up the
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polarity of the out going control signals <PRE> I_POL 0 Inverts Interlace Flag 0
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N_POL 1 Inverts NTSC Flag 0
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K_POL 2 Inverts Burst Blank Flag 0
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B_POL 3 Inverts Burst Flag 0
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H_POL 4 Inverts HSyncb Flag 0
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V_POL 5 Inverts VSyncb Flag 0
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F_POL 6 Inverts Field Flag 0
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C_POL 7 Inverts CSyncb Flag 0
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</PRE><BR><b>Horizontal Scale Register</b> (R/W) <BR><BR>This register sets up the
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step size of the horizontal stepper. <PRE> STP 8:0 Horizontal stepping size (U1.8). 256
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HS_EN 12 Horizontal Scaler Enable 0
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</PRE><BR><b>Scaling Width Register</b> (R/W) <BR><BR>This register is the number
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of source pixels to be scaled. This is only used when the Horizontal Scaler is
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enabled. For example, if the image is to be scaled from 320x240 to 640x240, 320
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would be written into this register. <PRE> SRCWIDTH 9:0 Horizontal stepping size 0
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</PRE><BR><b>Filter Coefficient Table 0</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC00204C</font></b><BR><BR>This register sets up
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part of the low pass filter. Taps 0 to 9 are in the range [0.0, 2.0). <PRE> T0 9:0 Tap 0 (U1.9). -
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T1 19:10 Tap 1. -
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T2 29:20 Tap 2. -
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</pre><b>Filter Coefficient Table 1</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC002050</font></b><br><br>
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This register sets up part of the low pass filter.<pre>
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T3 9:0 Tap 3. -
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T4 19:10 Tap 4. -
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T5 29:20 Tap 5. -
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</pre><b>Filter Coefficient Table 2</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC002054</font></b><br><br>
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This register sets up part of the low pass filter.<pre>
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T6 9:0 Tap 6. -
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T7 19:10 Tap 7. -
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T8 29:20 Tap 8. -
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</pre><b>Filter Coefficient Table 3</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC002058</font></b><br><br>
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This register sets up part of the low pass filter. Taps 9 to tap 24
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are in the range [-0.125, 0.125).<pre>
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T9 7:0 Tap 9 (S-2.9). -
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T10 15:8 Tap 10. -
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T11 23:16 Tap 11. -
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T12 31:24 Tap 12. -
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</pre><b>Filter Coefficient Table 4</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC00205C</font></b><br><br>
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This register sets up part of the low pass filter.<pre>
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T13 7:0 Tap 13. -
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T14 15:8 Tap 14. -
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T15 23:16 Tap 15. -
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T16 31:24 Tap 16. -
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</pre><b>Filter Coefficient Table 5</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC002060</font></b><br><br>
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This register sets up part of the low pass filter.<pre>
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T17 7:0 Tap 17. -
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T18 15:8 Tap 18. -
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T19 23:16 Tap 19. -
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T20 31:24 Tap 20. -
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</pre><b>Filter Coefficient Table 6</b> (R/W) [32] <b><font face=Verdana color=PURPLE size=2pt>CC002064</font></b><br><br>
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This register sets up part of the low pass filter.<pre>
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T21 7:0 Tap 21. -
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T22 15:8 Tap 22. -
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T23 23:16 Tap 23. -
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T24 31:24 Hardwired to zero. -
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</PRE>
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<br><b><B>VI Clock Select Register</b></B> (R/W) [16] <b><font face=Verdana color=PURPLE size=2pt>CC00206C</font></b><br><br>
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This register selects whether the VI will receive a 27 Mhz or a 54 Mhz
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clock. The 54 Mhz clock is used only with the progressive
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display modes.<PRE>
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VICLKSEL 1 0 for 27 Mhz video clk 0
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1 for 54 Mhz video clk
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</PRE>
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<br><b>VI DTV Status Register</b> (R) [16] <b><font face=Verdana color=PURPLE size=2pt>CC00206E</font></b><br><br>
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This register allows software to read the status of two I/O pins.<PRE>
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VISEL 2 Don't care -
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</PRE><BR><b>Border HBE</b> (R/W) [16] <b><font face=Verdana color=PURPLE size=2pt>CC002072</font></b><BR><BR>This register (in conjunction with the
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border HBS) sets up a black border around the actual active pixels in debug
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mode. This was done in order to accommodate certain encoders that only support
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720 active pixels. The border HBE and HBS can be programmed for 720 active
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pixels while the regular HBE and HBS can be programmed to the actual active
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width. This allows the frame buffer to be of any width without having to
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manually set up a border in memory. These registers will only take effect if
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enabled and in debug mode. <PRE> HBE656 9:0 Border Horizontal Blank End 0
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BRDR_EN 15 Border Enable 0
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</PRE><BR><b>Border HBS</b> (R/W) [16] <b><font face=Verdana color=PURPLE size=2pt>CC002074</font></b> <PRE> HBS656 9:0 Border Horizontal Blank Start 0
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</PRE>
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<br><i> * The fourth column in each table shows the power-up reset values.</i><br>
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<i> ** All numbers are little-endian (PPC using big-endian!) .</i><br><br>
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<hr>
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<br><i>
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Ripped from USPTO #6609977<br>
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<a href="mailto:ogamespec@gmail.com">org - ogamespec@gmail.com</a></i>
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