GAMECUBE Video Interface
Vertical Timing Register (R/W) [16] CC002000
This register setups the
vertical timing. The value ACV is double buffered EQU 3:0 Equalization pulse in half lines. -
ACV 13:4 Active video in full lines. -
Display Configuration Register (R/W) [16] CC002002
This register set ups and enables VI. Generally, VI
should be reset before enabling it. This resets the states into some known
values. ENB 0 This bit enables the video timing generation and data request. 0
RST 1 This bit clears all data request and puts VI into its idle state. 0
NIN 2 To select interlace or non-interlace mode. NIN = 0: interlace, 0
NIN = 1: non-interlace. In non-interlace mode, the top field is
drawn at field rate while the bottom field is not displayed.
DLR 3 This bit selects the 3D display mode.
LE0 5:4 Gun trigger mode. It enables the Display Latch Register 0. When 0
the mode is 1 or 2, it will clear itself(off) automatically when a
gun trigger is detected or at time out. This field is double buffered.
0 off
1 on for 1 field
2 on for 2 fields
3 always on
LE1 7:6 To enable Display Latch Register 1. See the description of LE0. 0
FMT 9:8 Indicates current video format: 0
0 NTSC
1 PAL
2 MPAL
3 Debug (CCIR656)
Horizontal Timing 0 Register (R/W) [32] CC002004
This register setups
the horizontal timing. HLW 9:0 Half line width. -
HCE 22:16 Horizontal sync start to color burst end. -
HCS 30:24 Horizontal sync start to color burst start. -
Horizontal Timing 1 Register (R/W) [32] CC002008
This register setups
the horizontal timing. HSY 6:0 Horizontal sync width. -
HBE 16:7 Horizontal sync start to horizontal blanking end. -
HBS 26:17 Half line to horizontal blanking start. -
Odd Field Vertical Timing Register (R/W) [32] CC00200C
This register
sets up the pre-blanking and post-blanking intervals of odd fields. The values
PRB and PSB are double buffered. PRB 9:0 Pre-blanking in half lines. -
PSB 25:16 Post-blanking in half lines. -
Even Field Vertical Timing Register (R/W) [32] CC002010
This register
sets up the pre-blanking and post-blanking intervals of even fields. The values
PRB and PSB are double buffered. PRB 9:0 Pre-blanking in half lines. -
PSB 25:16 Post-blanking in half lines. -
Odd Field Burst Blanking Interval Register (R/W) [32] CC002014
This
register sets up the burst blanking interval of odd fields. BS1 4:0 Field 1 start to burst blanking start in half lines. -
BE1 15:5 Field 1 start to burst blanking end in half lines. -
BS3 20:16 Field 3 start to burst blanking start in half lines. -
BE3 31:21 Field 3 start to burst blanking end in half lines. -
Even Field Burst Blanking Interval Register (R/W) [32] CC002018
This
register sets up the burst-blanking interval of even fields. BS2 4:0 Field 2 start to burst blanking start in half lines. -
BE2 15:5 Field 2 start to burst blanking end in half lines. -
BS4 20:16 Field 4 start to burst blanking start in half lines. -
BE4 31:21 Field 4 start to burst blanking end in half lines. -
Top Field Base Register L (R/W) [32] CC00201C
This register specifies
the display origin of the top field of a picture in 2D display mode or for the
left picture in 3D display mode. FBB 23:0 External memory address of the frame buffer image. -
XOF 27:24 Horizontal offset, in pixels, of the left-most pixel -
within the first word of the fetched picture. -
Top Field Base Register R (R/W) [32] CC002020
This register specifies
the base address of the top field for the right picture in the 3D display mode.
It is not used in 2D display mode. FBB 23:0 External memory address of the frame buffer image. -
Bottom Field Base Register L (R/W) [32] CC002024
This register specifies
the display origin of the bottom field of a picture in 2D display mode or for
the left picture in 3D display mode. FBB 23:0 External memory address of the frame buffer image. -
Bottom Field Base Register R (R/W) [32] CC002028
This register specifies
the base address of the bottom field for the right picture in the 3D display
mode. It is not used in 2D display mode. FBB 23:0 External memory address of the frame buffer image. -
Picture Configuration Register (R/W)
This register
specifies the picture configuration. STD 7:0 Stride per line in words. -
WPL 14:8 Number of reads per line in words. -
Display Position Register (R) [32] CC00202C
This register contains the
current raster position.
The Horizontal Count is in pixels and runs from
1 to # pixels per line. It is reset to 1 at the beginning of every line.
The Vertical Count is in lines (on a frame basis) and runs from 1 to #
lines per frame. It is 1 at the beginning of pre-equalization. This is a frame
line count. So for example: for NTSC vcount=264 is the first (full) line in the
second field and vcount=525 is the last line in the frame (fields being numbered
1-4). For non-interlaced modes vcount is on a field-by-field basis (for NTSC
vcount ranges from 1-263).
This counting scheme applies the Display
Position, Display Interrupt, and Display Latch registers. HCT 10:0 Horizontal count. -
VCT 26:16 Vertical count. -
Display Interrupt Register 0 (R/W) [32] CC002030
There are a total of
four display interrupt registers (0-3). They are used to generate interrupts to
the main processor at different positions within a field. Each register has a
separate enable bit. The interrupt is cleared by writing a zero to the status
flag (INT). HCT 10:0 Horizontal count to generate interrupt. -
VCT 26:16 Vertical count to generate interrupt. -
ENB 28 Interrupt is enabled if this bit is set. 0
INT 31 Interrupt status. A "1" indicates that an interrupt 0
is active.
Display Interrupt Register 1 (R/W) [32] CC002034
See the description of
Display Interrupt Register 0.
Display Interrupt Register 2 (R/W)
[32] CC002038
See the description of Display Interrupt Register 0.
Display
Interrupt Register 3 (R/W) [32] CC00203C
See the description of Display Interrupt
Register 0.
Display Latch Register 0 (R/W)
The Display Latch
Register 0 latches the value of the Display Position Register at the rising edge
of the gt0 signal. The trigger flag is set if a gun trigger is detected. Writing
a zero to the register clear the trigger flag. HCT 10:0 Horizontal count. 0
VCT 26:16 Vertical count. 0
TRG 31 Trigger flag. 0
Display Latch Register 1 (R/W)
See the description of
Display Latch Register 0. This register is latched on the rising edge of the gt1
signal.
Output Polarity Register (R/W)
This register sets up the
polarity of the out going control signals I_POL 0 Inverts Interlace Flag 0
N_POL 1 Inverts NTSC Flag 0
K_POL 2 Inverts Burst Blank Flag 0
B_POL 3 Inverts Burst Flag 0
H_POL 4 Inverts HSyncb Flag 0
V_POL 5 Inverts VSyncb Flag 0
F_POL 6 Inverts Field Flag 0
C_POL 7 Inverts CSyncb Flag 0
Horizontal Scale Register (R/W)
This register sets up the
step size of the horizontal stepper. STP 8:0 Horizontal stepping size (U1.8). 256
HS_EN 12 Horizontal Scaler Enable 0
Scaling Width Register (R/W)
This register is the number
of source pixels to be scaled. This is only used when the Horizontal Scaler is
enabled. For example, if the image is to be scaled from 320x240 to 640x240, 320
would be written into this register. SRCWIDTH 9:0 Horizontal stepping size 0
Filter Coefficient Table 0 (R/W) [32] CC00204C
This register sets up
part of the low pass filter. Taps 0 to 9 are in the range [0.0, 2.0). T0 9:0 Tap 0 (U1.9). -
T1 19:10 Tap 1. -
T2 29:20 Tap 2. -
Filter Coefficient Table 1 (R/W) [32] CC002050
This register sets up part of the low pass filter.
T3 9:0 Tap 3. -
T4 19:10 Tap 4. -
T5 29:20 Tap 5. -
Filter Coefficient Table 2 (R/W) [32] CC002054
This register sets up part of the low pass filter.
T6 9:0 Tap 6. -
T7 19:10 Tap 7. -
T8 29:20 Tap 8. -
Filter Coefficient Table 3 (R/W) [32] CC002058
This register sets up part of the low pass filter. Taps 9 to tap 24
are in the range [-0.125, 0.125).
T9 7:0 Tap 9 (S-2.9). -
T10 15:8 Tap 10. -
T11 23:16 Tap 11. -
T12 31:24 Tap 12. -
Filter Coefficient Table 4 (R/W) [32] CC00205C
This register sets up part of the low pass filter.
T13 7:0 Tap 13. -
T14 15:8 Tap 14. -
T15 23:16 Tap 15. -
T16 31:24 Tap 16. -
Filter Coefficient Table 5 (R/W) [32] CC002060
This register sets up part of the low pass filter.
T17 7:0 Tap 17. -
T18 15:8 Tap 18. -
T19 23:16 Tap 19. -
T20 31:24 Tap 20. -
Filter Coefficient Table 6 (R/W) [32] CC002064
This register sets up part of the low pass filter.
T21 7:0 Tap 21. -
T22 15:8 Tap 22. -
T23 23:16 Tap 23. -
T24 31:24 Hardwired to zero. -
VI Clock Select Register (R/W) [16] CC00206C
This register selects whether the VI will receive a 27 Mhz or a 54 Mhz
clock. The 54 Mhz clock is used only with the progressive
display modes.
VICLKSEL 1 0 for 27 Mhz video clk 0
1 for 54 Mhz video clk
VI DTV Status Register (R) [16] CC00206E
This register allows software to read the status of two I/O pins.
VISEL 2 Don't care -
Border HBE (R/W) [16] CC002072
This register (in conjunction with the
border HBS) sets up a black border around the actual active pixels in debug
mode. This was done in order to accommodate certain encoders that only support
720 active pixels. The border HBE and HBS can be programmed for 720 active
pixels while the regular HBE and HBS can be programmed to the actual active
width. This allows the frame buffer to be of any width without having to
manually set up a border in memory. These registers will only take effect if
enabled and in debug mode. HBE656 9:0 Border Horizontal Blank End 0
BRDR_EN 15 Border Enable 0
Border HBS (R/W) [16] CC002074 HBS656 9:0 Border Horizontal Blank Start 0
* The fourth column in each table shows the power-up reset values.
** All numbers are little-endian (PPC using big-endian!) .
Ripped from USPTO #6609977
org - ogamespec@gmail.com