Commit graph

12301 commits

Author SHA1 Message Date
Unknown W. Brackets
fcc90095f7 riscv: Enable block linking. 2023-08-12 09:37:02 -07:00
Unknown W. Brackets
247788806a irjit: Add direct helper for start PC.
It's annoying always fetching length too.
2023-08-12 09:37:02 -07:00
Unknown W. Brackets
b3cdf06c5a riscv: Write fixup on block invalidation. 2023-08-12 09:37:02 -07:00
Unknown W. Brackets
3757ebca2d irjit: Invalidate/finalize target blocks.
Doesn't actually do anything yet, but adds plumbing.
2023-08-12 09:37:02 -07:00
Henrik Rydgård
50ea506b6a Revert "Regression experiment: Temporarily revert to returning 0 from bad achievement memory accesses."
This reverts commit a044d8ccc2.
2023-08-09 16:16:39 +02:00
Henrik Rydgård
2342c4522c
Merge pull request #17875 from unknownbrackets/riscv-jit
RISC-V: Implement a few more ops
2023-08-09 09:30:15 +02:00
Henrik Rydgård
bac4e8d42d
Merge pull request #17874 from unknownbrackets/irjit-exits
IR: Simplify exits to ExitToConst when viable
2023-08-09 09:11:52 +02:00
Henrik Rydgård
6758675054
Merge pull request #17873 from unknownbrackets/irjit-shuffle
IR: Fix vqmul / Vec4Shuffle overlap
2023-08-09 09:10:03 +02:00
Unknown W. Brackets
2c13b6d973 riscv: Implement vc2i. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets
28c58c1d24 irjit: Allow more forms of vmidt.
Mildly worth it.
2023-08-08 23:17:32 -07:00
Unknown W. Brackets
4b9011e475 riscv: Reduce call bloat using temps. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets
ddf3d02a3c riscv: Implement vi2uc. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets
268adf1aa1 riscv: Implement scaled float/int convert. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets
0b4e7d60f9 riscv: Implement ReverseBits in jit. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets
ad4cbbab8e riscv: Don't cache mipState on backend.
Bad sign if we're trying to use it, anyway.
2023-08-08 23:17:32 -07:00
Unknown W. Brackets
31ff23746c irjit: Prefer ExitToConst over ExitToReg. 2023-08-08 23:14:01 -07:00
Unknown W. Brackets
3f97545f99 irjit: Reduce exits from constants.
This reduces bloat a bit, and may help with common funcs that enter short
loops.
2023-08-08 23:05:14 -07:00
Unknown W. Brackets
5f9a8fd1a1 irjit: Rename IRRegCache to IRImmRegCache.
For clarity, since it's not a native regcache.
2023-08-08 23:05:14 -07:00
Unknown W. Brackets
1a92027810 riscv: Make Vec4Shuffle overlap safe. 2023-08-08 23:00:45 -07:00
Unknown W. Brackets
e73c203984 irjit: Fix Vec4Shuffle overlap issue. 2023-08-08 23:00:39 -07:00
Henrik Rydgård
ac269aaa4b rcheevos: revert to before #17806
PR #17806 upgraded rcheevos, after which a regression is reported in
issue #17631.

Experimentally revert to confirm.
2023-08-08 15:38:22 +02:00
Henrik Rydgård
a044d8ccc2 Regression experiment: Temporarily revert to returning 0 from bad achievement memory accesses. 2023-08-08 15:33:46 +02:00
Henrik Rydgård
5ee04ce403 SDL: Break out event processing from main loop
Makes things a bit easier to work with.
2023-08-08 12:28:42 +02:00
Henrik Rydgård
bcae36d8cb Merge NativeUpdate and NativeRender, we always call them together. 2023-08-07 22:50:57 +02:00
Henrik Rydgård
096c168dd7
Add yield() function to tell the CPU that we're busy-waiting (rare) (#17862)
* Add yield() function to tell the CPU that we're busy-waiting (rare)

Use it only for the busy-wait in lag sync, which only happens in
Windows.

* Buildfix attempt
2023-08-07 21:38:03 +02:00
Henrik Rydgård
e9431d0d1e
Merge pull request #17859 from unknownbrackets/irjit-vec4
irjit: Use Vec4 a bit more
2023-08-06 23:05:33 +02:00
Unknown W. Brackets
3dc71cff75 irjit: Keep a couple more ops in Vec4. 2023-08-06 13:46:24 -07:00
Unknown W. Brackets
6a1dbd4cde irjit: Allow Vec4 to be used with masks. 2023-08-06 13:46:24 -07:00
Unknown W. Brackets
2b964fd3b0 irjit: Handle more common Vec4 prefix cases. 2023-08-06 13:38:00 -07:00
Unknown W. Brackets
79ca880ac7 irjit: Implement vqmul, add Vec4Blend.
Should be useful more places.
2023-08-06 13:38:00 -07:00
Unknown W. Brackets
85ee7c85c1 irjit: Allow masked vneg.q. 2023-08-06 13:38:00 -07:00
Henrik Rydgård
d90dbcb28e
Merge pull request #17857 from unknownbrackets/ir-vfpuctrl
irjit: Fix mfvc eating prefixes
2023-08-06 17:56:22 +02:00
Unknown W. Brackets
a32889d3ca irjit: Consistently dirty vfpuctrl in IR. 2023-08-06 08:36:19 -07:00
Unknown W. Brackets
a29a35b91a irjit: Fix mfvc eating prefixes.
It doesn't and shouldn't, which is why it's marked as not.
2023-08-06 08:28:25 -07:00
Henrik Rydgård
70622e0d4e
Merge pull request #17853 from Nemoumbra/buildfix
Buildfix for VS2017
2023-08-06 14:29:04 +02:00
Nemoumbra
c2f9ae2e16 Buildfix for VS2017 2023-08-06 15:06:54 +03:00
Henrik Rydgård
ea659319b2
Merge pull request #17852 from unknownbrackets/riscv-centralize
IR: centralize common parts of native backend
2023-08-06 10:54:53 +02:00
Unknown W. Brackets
93e3d35f5d irjit: Move more to IRNativeBackend, split. 2023-08-06 00:16:43 -07:00
Unknown W. Brackets
691799a0ca irjit: Centralize native jit compile dispatch. 2023-08-03 23:14:58 -07:00
Henrik Rydgård
a32249a3cf Move DebugOverlay rendering to the overlay screen, allowing drawing it on top of the menu 2023-08-03 16:19:18 +02:00
Henrik Rydgård
ece6a505b3
Merge pull request #17837 from hrydgard/frame-history
Vulkan: Keep track of a short history of some timestamps in each frame
2023-08-02 17:06:55 +02:00
Hoe Hao Cheng
805821e01e Core: decouple UpdateScreenScale from preprocessor defines 2023-08-02 22:34:46 +08:00
Hoe Hao Cheng
0d7a1831b6 sdl: support HiDPI on wayland 2023-08-02 22:34:46 +08:00
Henrik Rydgård
cda59e8510 Vulkan: Keep track of some timestamps in a frame 2023-08-02 16:25:17 +02:00
Henrik Rydgård
0b4fee1259 One too much 2023-08-02 14:07:47 +02:00
Henrik Rydgård
c3511529e4 Somehow forgot to delete some unused bools 2023-08-02 14:07:05 +02:00
Henrik Rydgård
fc6879674e Refactor overlays into an enum 2023-08-02 13:03:04 +02:00
Henrik Rydgård
9a8919810b Translation cleanups 2023-08-01 13:04:52 +02:00
Henrik Rydgård
f45176fd25 Allow configuring in which corner achievement notifications can show up. 2023-08-01 12:52:09 +02:00
Henrik Rydgård
1071e1f248 Move towards separate types for leaderboard events 2023-08-01 11:57:28 +02:00