Unknown W. Brackets
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ef1dc583a2
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Fix various minor warnings.
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2016-03-20 14:17:51 -07:00 |
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Henrik Rydgård
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c1b91ff5c1
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x86: Add a way to eliminate some mov instructions.
Not currently used yet.
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2015-04-12 13:50:23 -07:00 |
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Unknown W. Brackets
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179e996b0b
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jit: Discard unused regs before a syscall.
This is a pretty minor optimization, though.
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2015-03-01 11:08:59 -08:00 |
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Chin
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37f50a3792
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Change to pass some arguments by reference
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2015-03-01 16:49:00 +01:00 |
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Unknown W. Brackets
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77777e372d
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x86jit: Use R15 when safe for the jit.
This is virtually always safe.
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2014-12-17 08:09:59 -08:00 |
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Unknown W. Brackets
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afdbf5610b
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jit: Use nicknames for a few more static regs.
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2014-12-17 01:11:33 -08:00 |
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Henrik Rydgard
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05a8e2e35d
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Some work towards being able to build two JITs together
This will be useful for testing/debugging, but not there yet.
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2014-12-13 21:13:54 +01:00 |
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Unknown W. Brackets
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f817d49dfb
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jit: Discard clobbered registers on spill.
If we're spilling anyway, discard rather than saving.
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2014-12-07 23:08:21 -08:00 |
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Unknown W. Brackets
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eeff110c0f
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jit: Improve and unify GPR spill logic.
Now the same logic on x86 and ARM, and handles HI/LO/etc. better.
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2014-12-07 21:10:28 -08:00 |
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Unknown W. Brackets
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9dd6bb56bb
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jit: Make available js_ and jo_ in regcaches.
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2014-12-07 21:07:23 -08:00 |
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Henrik Rydgard
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51d55bd645
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Namespacing cleanup (it's bad to do "using namespace" in a header)
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2014-12-07 14:44:15 +01:00 |
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Henrik Rydgard
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1c78e29c79
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x86 jit: For clarity, use TEMPREG where it doesn't matter that it's EAX.
Might have missed a few places.
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2014-11-16 17:38:26 +01:00 |
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Henrik Rydgård
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eab010a0c0
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x86 JIT: Sacrifice a register for a pointer to the MIPS context. Shrinks emitted x86 code considerably.
Nice in 64-bit, but might be a bit too much in 32-bit though... Needs testing.
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2014-10-12 19:35:55 +02:00 |
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Unknown W. Brackets
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27870aa593
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x86jit: Map HI/LO as registers.
Not actually ever cached, but now it's all consistent.
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2014-06-28 00:38:56 -07:00 |
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Unknown W. Brackets
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acad2e1763
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x86jit: Cache fpcond in a register.
Mostly to match armjit.
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2014-06-28 00:38:55 -07:00 |
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Unknown W. Brackets
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fd38b10ab6
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x86jit: Rename imm funcs to match armjit.
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2013-11-10 21:59:49 -08:00 |
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Henrik Rydgard
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5ad04a23f4
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x86 jit: Rename BindToRegister to MapReg
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2013-11-09 15:23:31 +01:00 |
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Unknown W. Brackets
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97aa1a631e
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Improve typesafety in the x86 regalloc.
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2013-08-24 19:41:10 -07:00 |
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Unknown W. Brackets
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52d6080fb4
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Pass in some analysis results, don't use yet.
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2013-08-24 15:36:24 -07:00 |
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Unknown W. Brackets
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64c2ea86c0
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Add a method to save the gpr/fpr state in jit.
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2013-08-16 00:12:49 -07:00 |
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Henrik Rydgard
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3b9e6243eb
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Only flush the required registers on function calls (only implemented for real on ARM)
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2013-07-28 22:21:43 +02:00 |
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Henrik Rydgard
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68991511ee
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Split out the FPU reg cache into its own file too.
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2013-01-26 01:34:19 +01:00 |
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Henrik Rydgard
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ad5e2b58c6
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Separate the two regcaches before doing major surgery to FPURegCache.
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2013-01-26 01:34:18 +01:00 |
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Unknown W. Brackets
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ce5f393fb8
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Hit immediates in the ALU better and more simply.
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2013-01-25 00:16:55 -08:00 |
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Henrik Rydgard
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64cc573703
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Switch to "GPL 2.0 or later" for various reasons. I wrote most of the code I imported from Dolphin (which is GPL2-but-not-later), so it should be OK.
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2012-11-04 23:24:00 +01:00 |
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Henrik Rydgard
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4f7ad15758
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Add snapshot of the whole source code.
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2012-11-01 16:19:01 +01:00 |
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