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jit: Make available js_ and jo_ in regcaches.

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This commit is contained in:
Unknown W. Brackets 2014-12-07 21:07:23 -08:00
parent 15d0a81122
commit 9dd6bb56bb
8 changed files with 28 additions and 13 deletions
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2
Core/MIPS/ARM/ArmJit.cpp
View file

@ -63,7 +63,7 @@ namespace MIPSComp
{
using namespace ArmGen;
ArmJit::ArmJit(MIPSState *mips) : blocks(mips, this), gpr(mips, &jo), fpr(mips, &js, &jo), mips_(mips)
ArmJit::ArmJit(MIPSState *mips) : blocks(mips, this), gpr(mips, &js, &jo), fpr(mips, &js, &jo), mips_(mips)
{
logBlocks = 0;
dontLogBlocks = 0;

4
Core/MIPS/ARM/ArmRegCache.cpp
View file

@ -28,7 +28,7 @@
using namespace ArmGen;
ArmRegCache::ArmRegCache(MIPSState *mips, MIPSComp::ArmJitOptions *options) : mips_(mips), options_(options) {
ArmRegCache::ArmRegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::ArmJitOptions *jo) : mips_(mips), js_(js), jo_(jo) {
}
void ArmRegCache::Init(ARMXEmitter *emitter) {
@ -55,7 +55,7 @@ const ARMReg *ArmRegCache::GetMIPSAllocationOrder(int &count) {
// R8 is used to preserve flags in nasty branches.
// R9 and upwards are reserved for jit basics.
// R14 (LR) is used as a scratch reg (overwritten on calls/return.)
if (options_->downcountInRegister) {
if (jo_->downcountInRegister) {
static const ARMReg allocationOrder[] = {
R1, R2, R3, R4, R5, R6, R12,
};

6
Core/MIPS/ARM/ArmRegCache.h
View file

@ -75,11 +75,12 @@ enum {
namespace MIPSComp {
struct ArmJitOptions;
struct JitState;
}
class ArmRegCache {
public:
ArmRegCache(MIPSState *mips, MIPSComp::ArmJitOptions *options);
ArmRegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::ArmJitOptions *jo);
~ArmRegCache() {}
void Init(ArmGen::ARMXEmitter *emitter);
@ -132,8 +133,9 @@ private:
ArmGen::ARMReg FindBestToSpill(bool unusedOnly);
MIPSState *mips_;
MIPSComp::ArmJitOptions *options_;
ArmGen::ARMXEmitter *emit_;
MIPSComp::JitState *js_;
MIPSComp::ArmJitOptions *jo_;
u32 compilerPC_;
enum {

5
Core/MIPS/x86/Jit.cpp
View file

@ -133,7 +133,6 @@ Jit::Jit(MIPSState *mips) : blocks(mips, this), mips_(mips)
blocks.Init();
gpr.SetEmitter(this);
fpr.SetEmitter(this);
fpr.SetOptions(&jo);
AllocCodeSpace(1024 * 1024 * 16);
asm_.Init(mips, this);
safeMemFuncs.Init(&thunks);
@ -419,8 +418,8 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
MIPSAnalyst::AnalysisResults analysis = MIPSAnalyst::Analyze(em_address);
gpr.Start(mips_, analysis);
fpr.Start(mips_, analysis);
gpr.Start(mips_, &js, &jo, analysis);
fpr.Start(mips_, &js, &jo, analysis);
js.numInstructions = 0;
while (js.compiling) {

5
Core/MIPS/x86/RegCache.cpp
View file

@ -52,7 +52,7 @@ GPRRegCache::GPRRegCache() : mips(0), emit(0) {
memset(xregs, 0, sizeof(xregs));
}
void GPRRegCache::Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats) {
void GPRRegCache::Start(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo, MIPSAnalyst::AnalysisResults &stats) {
this->mips = mips;
for (int i = 0; i < NUM_X_REGS; i++) {
xregs[i].free = true;
@ -85,6 +85,9 @@ void GPRRegCache::Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats) {
}*/
//Find top regs - preload them (load bursts ain't bad)
//But only preload IF written OR reads >= 3
js_ = js;
jo_ = jo;
}

9
Core/MIPS/x86/RegCache.h
View file

@ -56,12 +56,17 @@ struct GPRRegCacheState {
X64CachedReg xregs[NUM_X_REGS];
};
namespace MIPSComp {
struct JitOptions;
struct JitState;
}
class GPRRegCache
{
public:
GPRRegCache();
~GPRRegCache() {}
void Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats);
void Start(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo, MIPSAnalyst::AnalysisResults &stats);
void DiscardRegContentsIfCached(MIPSGPReg preg);
void SetEmitter(Gen::XEmitter *emitter) {emit = emitter;}
@ -116,4 +121,6 @@ private:
X64CachedReg xregs[NUM_X_REGS];
Gen::XEmitter *emit;
MIPSComp::JitState *js_;
MIPSComp::JitOptions *jo_;
};

5
Core/MIPS/x86/RegCacheFPU.cpp
View file

@ -35,7 +35,7 @@ FPURegCache::FPURegCache() : mips(0), initialReady(false), emit(0) {
vregs = regs + 32;
}
void FPURegCache::Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats) {
void FPURegCache::Start(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo, MIPSAnalyst::AnalysisResults &stats) {
this->mips = mips;
if (!initialReady) {
@ -46,6 +46,9 @@ void FPURegCache::Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats) {
memcpy(xregs, xregsInitial, sizeof(xregs));
memcpy(regs, regsInitial, sizeof(regs));
pendingFlush = false;
js_ = js;
jo_ = jo;
}
void FPURegCache::SetupInitialRegs() {

5
Core/MIPS/x86/RegCacheFPU.h
View file

@ -79,6 +79,7 @@ struct FPURegCacheState {
namespace MIPSComp {
struct JitOptions;
struct JitState;
}
enum {
@ -97,7 +98,7 @@ public:
FPURegCache();
~FPURegCache() {}
void Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats);
void Start(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo, MIPSAnalyst::AnalysisResults &stats);
void MapReg(int preg, bool doLoad = true, bool makeDirty = true);
void StoreFromRegister(int preg);
void StoreFromRegisterV(int preg) {
@ -117,7 +118,6 @@ public:
int GetTempVS(u8 *v, VectorSize vsz);
void SetEmitter(Gen::XEmitter *emitter) {emit = emitter;}
void SetOptions(MIPSComp::JitOptions *jo) {jo_ = jo;}
void Flush();
int SanityCheck() const;
@ -242,5 +242,6 @@ private:
static float tempValues[NUM_TEMPS];
Gen::XEmitter *emit;
MIPSComp::JitState *js_;
MIPSComp::JitOptions *jo_;
};