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2065 commits

Author SHA1 Message Date
Unknown W. Brackets
b24f84d1a2 interp: Handle prefixes on matrix init ops. 2019-03-31 17:11:24 -07:00
Unknown W. Brackets
59905de719 interp: Correct vsgn out of swizzle bounds. 2019-03-31 17:10:51 -07:00
Unknown W. Brackets
85ff32eed1 interp: Handle vsgn prefixing. 
One could compare against 3 using this, it just generates zeros to compare
with.
 2019-03-31 17:10:51 -07:00
Unknown W. Brackets
a5214d0b1a Jit: Ignore high bit in vmfvc/vmtvc. 2019-03-31 17:09:55 -07:00
Unknown W. Brackets
b881a689c4 interp: Ignore high bit in vmfvc/vmtvc. 
Both 0 and 128 read/write the S prefix, for example.
 2019-03-31 17:09:55 -07:00
Unknown W. Brackets
5736b1be2a interp: Correct some negative invalid zero cases. 
In these cases, the input value wires to +0.  Also, transposed the values
in a comment (oops.)
 2019-03-31 13:45:37 -07:00
Unknown W. Brackets
aa998b815c interp: Force vscmp result of invalid to zero. 
Some other ops do this, but mostly only that do plus or minus.
 2019-03-31 13:41:48 -07:00
Unknown W. Brackets
c7e83cd4fa interp: Correct vfim for -inf and similar. 
Was dropping the sign bit before for inf and nan.
 2019-03-31 13:41:48 -07:00
Unknown W. Brackets
5749ae09d0 interp: Correct vmfvc register behavior. 
The target and source registers were completely wrong.
 2019-03-31 13:41:48 -07:00
Unknown W. Brackets
b2e024025f interp: Handle wrong sizes of vf2h/vh2f. 
Probably not ever used, but they have consistent behavior.
 2019-03-31 13:41:48 -07:00
Unknown W. Brackets
aceb0a8244 interp: Correct vrnd prefix handling. 
We don't match random values perfectly anyway, but at least we should vary
at the right times.
 2019-03-31 13:41:48 -07:00
Unknown W. Brackets
dfc2449f35 interp: Match actual vdiv prefix handling. 2019-03-31 13:41:48 -07:00
Unknown W. Brackets
af3ed69144 interp: Mask moves to vfpu ctrl. 
These bits of the registers can't be written.
 2019-03-31 10:37:07 -07:00
Unknown W. Brackets
2a5d4e577d interp: Handle NAN more correctly in vscmp. 2019-03-31 10:37:07 -07:00
Unknown W. Brackets
db28c61272 interp: Handle flush prefixes slightly better. 2019-03-31 10:37:07 -07:00
Unknown W. Brackets
d40ac043d4 interp: Handle prefixes for Vmmov/Vmmul/Vmscl. 
I doubt any actual code uses this, but we have some tricky VFPU bugs left,
so just trying for maximum accuracy in the interpreter.
 2019-03-31 10:37:07 -07:00
Unknown W. Brackets
26b1368f7b interp: Handle vrot prefixes mostly correctly. 
Still some issues with 1/2 results and negate on swizzle.
 2019-03-31 10:37:07 -07:00
Unknown W. Brackets
8fd8dce185 interp: Use a helper to generate prefix consts. 
This makes more logical sense that using the VFPU_SWIZZLE and VFPU_ABS
macros to select the constant, although that's how the bits work.
 2019-03-31 10:33:26 -07:00
Unknown W. Brackets
b86a6af364 interp: Properly apply mask on single lane ops. 
When using something like vadd.s, we should still be applying the mask.
Mainly should only matter if masks are set in a conditional, or if games
nop out instructions.
 2019-03-31 10:13:28 -07:00
Unknown W. Brackets
1936e8c4d1 interp: Generate constants using prefixes. 
This way they properly respect negate in the S prefix.
 2019-03-31 10:13:28 -07:00
Unknown W. Brackets
0be3213151 interp: Correct vscl prefix handling. 2019-03-31 10:13:28 -07:00
Unknown W. Brackets
ec1dae57eb interp: Fix vbfy prefix handling. 2019-03-31 10:09:18 -07:00
Unknown W. Brackets
d5273f589a interp: Mask value in vpfxd. 
The actual register ends up with only the lower 12 bits, which makes sense
since those are the only ones that do anything.
 2019-03-31 08:23:36 -07:00
Unknown W. Brackets
9d1d4473e8 interp: Confirm vi2f/vf2i prefix handling. 2019-03-31 08:22:52 -07:00
Unknown W. Brackets
30223cb17f interp: Apply T prefix to D in vcmov. 2019-03-31 08:22:15 -07:00
Unknown W. Brackets
fef8e71b8f interp: Correct behavior for matrixes with size=1. 
Games don't (shouldn't?) actually use 1x1 matrices, but they seem to have
predictable behavior in matrix ops.
 2019-03-31 08:21:29 -07:00
Unknown W. Brackets
cfab70f149 interp: Handle abs/neg on nan values better. 
`fabsf` was altering other bits.
 2019-03-31 08:18:49 -07:00
Unknown W. Brackets
7dc775e54f IR: Use interp for unhandled prefix cases. 
The interpreter is not changed yet, so in theory this shouldn't change
behavior.
 2019-03-31 08:17:11 -07:00
Unknown W. Brackets
4c3aa841d3 IR: Correct vmmul optimizations. 
It's a bit confusing since it's not D = S*T, but rather D = S'*T.
 2019-03-23 15:31:10 -07:00
Unknown W. Brackets
aff1d8e8b2 interp: Implement vsbz and vlgb. 
Not sure any games actually use them, but good to have the remaining vfpu
ops all implemented.
 2019-02-23 15:08:49 -08:00
Unknown W. Brackets
520f850e09 Jit: Correct VFPU prefix eating flags. 
Verified by tests.  Also, confirmed that the old vxbz encoding had no
output, but the new position (as used by gas) does.
 2019-02-23 15:08:49 -08:00
Unknown W. Brackets
179ec61815 interp: Correctly handle vsocp prefixes. 
Very similar to vsop, just with a bit more fixed values.
 2019-02-23 10:05:13 -08:00
Unknown W. Brackets
6178a1fb33 Jit: Correct vocp prefix handling. 
See #5549.  Matches tests for various prefix settings.
 2019-02-23 09:15:26 -08:00
Henrik Rydgård
c80dd44da8 ARM/ARM64: Ignore invalid immediate addresses in delay slots, which may be conditional. 
Should do something in x86's safe mem too, but leaving for later.

Replaces #11824
 2019-02-23 10:15:09 +01:00
Unknown W. Brackets
d7f40afd9d interp: Correct vocp prefix handling. 
Also, guess that vsocp also applies prefixes.  See #5549.
 2019-02-21 19:02:16 -08:00
Henrik Rydgard
a802adb1f6 Add simple UI for JIT feature disable flags 2019-02-04 13:00:08 +01:00
Unknown W. Brackets
419c1fbd73 Jit: Respect flags for jit types and features. 
Left some free space for more.
 2019-02-03 14:57:08 -08:00
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46649a218e Core: Add flags to disable jit features. 
Not actually disabling yet, just setup.
 2019-02-03 13:58:24 -08:00
pent0
4a53853f79 Update UWP port 2018-12-10 20:55:07 +07:00
Unknown W. Brackets
8506da14f0 Debugger: Prevent invalid address on syscall. 2018-11-17 08:54:29 -08:00
Unknown W. Brackets
8ae157e27f Debugger: Update to latest armips. 2018-06-30 14:18:26 -07:00
Unknown W. Brackets
b4496f1975 Core: Move config enums to separate file. 
These are a bit strewn about and there are constants that aren't
consistently used, which just adds confusion.
 2018-06-23 10:59:18 -07:00
Unknown W. Brackets
b114656321 Debugger: Allow conditions on threadID/moduleID. 
And now step over/out/into can tie to the correct thread.
 2018-06-08 06:59:18 -07:00
Unknown W. Brackets
b2cc4a0965 Debugger: Add memory breakpoint management. 2018-06-08 06:59:18 -07:00
Unknown W. Brackets
22940f0393 Debugger: Avoid asserts in disassembly. 2018-06-08 06:59:18 -07:00
Unknown W. Brackets
98cddad73a Debugger: Minor cleanup in MIPSDebugInterface. 2018-06-08 06:59:16 -07:00
Unknown W. Brackets
4c3fe47372 jit: Remove unused breakpoint code. 2018-06-06 17:31:56 -07:00
Unknown W. Brackets
5510a69d41 armjit: Enable breakpoints. 2018-06-06 17:31:56 -07:00
Unknown W. Brackets
eb4b59b530 arm64jit: Enable breakpoints. 
Memory breakpoints not yet really tested.
 2018-06-06 17:31:56 -07:00
Henrik Rydgård
f9cfb05895
Merge pull request #10987 from unknownbrackets/debugger-core 
Improve debugger threadsafety and consistency
 2018-06-06 21:10:14 +02:00