21 commits

Author	SHA1	Message	Date
Unknown W. Brackets	81aeb04788	arm64jit: Implement Vec4Blend.	2023-09-05 00:10:26 -07:00
Unknown W. Brackets	9439a43323	riscv: Correct an overlap case, fix assert.	2023-09-03 13:29:57 -07:00
Unknown W. Brackets	6a75e6712e	riscv: Use automapping for special cases too.	2023-08-20 12:42:11 -07:00
Unknown W. Brackets	a190793ad2	riscv: Simplify mapping for more instructions.	2023-08-20 12:42:11 -07:00
Unknown W. Brackets	f9bf7de701	riscv: Use a single reg cache.	2023-08-20 12:42:11 -07:00
Unknown W. Brackets	a23ade8f75	riscv: Map IR regs based on metadata. ... Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.	2023-08-20 12:42:11 -07:00
Unknown W. Brackets	4e41f83ecc	riscv: Centralize IR reg cache metadata checks. ... These are all largely the same between backends.	2023-08-17 23:03:31 -07:00
Unknown W. Brackets	b30daa5760	riscv: Centralize state of regcaches.	2023-08-15 21:51:38 -07:00
Unknown W. Brackets	52cc38bf2a	riscv: Implement vs2i.	2023-08-13 18:27:19 -07:00
Henrik Rydgård	2342c4522c	Merge pull request #17875 from unknownbrackets/riscv-jit ... RISC-V: Implement a few more ops	2023-08-09 09:30:15 +02:00
Unknown W. Brackets	2c13b6d973	riscv: Implement vc2i.	2023-08-08 23:17:32 -07:00
Unknown W. Brackets	ddf3d02a3c	riscv: Implement vi2uc.	2023-08-08 23:17:32 -07:00
Unknown W. Brackets	1a92027810	riscv: Make Vec4Shuffle overlap safe.	2023-08-08 23:00:45 -07:00
Unknown W. Brackets	79ca880ac7	irjit: Implement vqmul, add Vec4Blend. ... Should be useful more places.	2023-08-06 13:38:00 -07:00
Unknown W. Brackets	93e3d35f5d	irjit: Move more to IRNativeBackend, split.	2023-08-06 00:16:43 -07:00
Unknown W. Brackets	921bd2391c	riscv: Implement vi2s.	2023-07-29 19:02:15 -07:00
Unknown W. Brackets	0c9dce8ba8	riscv: Implement vec4 dot.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	23e9dffc68	riscv: Implement vec4 shuffle and init.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	4e17c59cc2	riscv: Implement simple vec4 ops via floats.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	c2da7d18bb	riscv: Stub out more IR compilation categories.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	bf7a6eb2cd	riscv: Add jit for some initial instructions.	2023-07-23 18:01:00 -07:00