mirror of
https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
346 lines
10 KiB
C++
346 lines
10 KiB
C++
// Copyright (c) 2023- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include <algorithm>
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#include "Core/MemMap.h"
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#include "Core/MIPS/RiscV/RiscVJit.h"
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#include "Core/MIPS/RiscV/RiscVRegCache.h"
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// This file contains compilation for vector instructions.
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//
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE. No flags because that's in IR already.
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// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
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#define CONDITIONAL_DISABLE {}
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#define DISABLE { CompIR_Generic(inst); return; }
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#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
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namespace MIPSComp {
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using namespace RiscVGen;
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using namespace RiscVJitConstants;
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void RiscVJitBackend::CompIR_VecAssign(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Vec4Init:
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for (int i = 0; i < 4; ++i)
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fpr.SpillLock(inst.dest + i);
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for (int i = 0; i < 4; ++i)
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fpr.MapReg(inst.dest + i, MIPSMap::NOINIT);
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for (int i = 0; i < 4; ++i)
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fpr.ReleaseSpillLock(inst.dest + i);
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// TODO: Check if FCVT/FMV/FL is better.
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switch ((Vec4Init)inst.src1) {
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case Vec4Init::AllZERO:
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for (int i = 0; i < 4; ++i)
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FCVT(FConv::S, FConv::W, fpr.R(inst.dest + i), R_ZERO);
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break;
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case Vec4Init::AllONE:
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LI(SCRATCH1, 1.0f);
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FMV(FMv::W, FMv::X, fpr.R(inst.dest), SCRATCH1);
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for (int i = 1; i < 4; ++i)
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FMV(32, fpr.R(inst.dest + i), fpr.R(inst.dest));
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break;
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case Vec4Init::AllMinusONE:
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LI(SCRATCH1, -1.0f);
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FMV(FMv::W, FMv::X, fpr.R(inst.dest), SCRATCH1);
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for (int i = 1; i < 4; ++i)
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FMV(32, fpr.R(inst.dest + i), fpr.R(inst.dest));
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break;
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case Vec4Init::Set_1000:
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LI(SCRATCH1, 1.0f);
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for (int i = 0; i < 4; ++i) {
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if (i == 0)
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FMV(FMv::W, FMv::X, fpr.R(inst.dest + i), SCRATCH1);
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else
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FCVT(FConv::S, FConv::W, fpr.R(inst.dest + i), R_ZERO);
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}
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break;
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case Vec4Init::Set_0100:
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LI(SCRATCH1, 1.0f);
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for (int i = 0; i < 4; ++i) {
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if (i == 1)
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FMV(FMv::W, FMv::X, fpr.R(inst.dest + i), SCRATCH1);
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else
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FCVT(FConv::S, FConv::W, fpr.R(inst.dest + i), R_ZERO);
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}
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break;
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case Vec4Init::Set_0010:
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LI(SCRATCH1, 1.0f);
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for (int i = 0; i < 4; ++i) {
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if (i == 2)
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FMV(FMv::W, FMv::X, fpr.R(inst.dest + i), SCRATCH1);
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else
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FCVT(FConv::S, FConv::W, fpr.R(inst.dest + i), R_ZERO);
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}
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break;
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case Vec4Init::Set_0001:
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LI(SCRATCH1, 1.0f);
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for (int i = 0; i < 4; ++i) {
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if (i == 3)
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FMV(FMv::W, FMv::X, fpr.R(inst.dest + i), SCRATCH1);
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else
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FCVT(FConv::S, FConv::W, fpr.R(inst.dest + i), R_ZERO);
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}
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break;
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}
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break;
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case IROp::Vec4Shuffle:
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if (inst.dest == inst.src1) {
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RiscVReg tempReg = fpr.Map4DirtyInTemp(inst.dest, inst.src1);
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// Try to find the least swaps needed to move in place, never worse than 6 FMVs.
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// Would be better with a vmerge and vector regs.
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int state[4]{ 0, 1, 2, 3 };
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int goal[4]{ (inst.src2 >> 0) & 3, (inst.src2 >> 2) & 3, (inst.src2 >> 4) & 3, (inst.src2 >> 6) & 3 };
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static constexpr int NOT_FOUND = 4;
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auto findIndex = [](int *arr, int val, int start = 0) {
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return (int)(std::find(arr + start, arr + 4, val) - arr);
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};
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auto moveChained = [&](const std::vector<int> &lanes, bool rotate) {
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int firstState = state[lanes.front()];
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if (rotate)
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FMV(32, tempReg, fpr.R(inst.dest + lanes.front()));
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for (size_t i = 1; i < lanes.size(); ++i) {
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FMV(32, fpr.R(inst.dest + lanes[i - 1]), fpr.R(inst.dest + lanes[i]));
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state[lanes[i - 1]] = state[lanes[i]];
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}
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if (rotate) {
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FMV(32, fpr.R(inst.dest + lanes.back()), tempReg);
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state[lanes.back()] = firstState;
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}
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};
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for (int i = 0; i < 4; ++i) {
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// Overlap, so if they match, nothing to do.
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if (goal[i] == state[i])
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continue;
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int neededBy = findIndex(goal, state[i], i + 1);
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int foundIn = findIndex(state, goal[i], 0);
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_assert_(foundIn != NOT_FOUND);
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if (neededBy == NOT_FOUND || neededBy == foundIn) {
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moveChained({ i, foundIn }, neededBy == foundIn);
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continue;
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}
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// Maybe we can avoid a swap and move the next thing into place.
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int neededByDepth2 = findIndex(goal, state[neededBy], i + 1);
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if (neededByDepth2 == NOT_FOUND || neededByDepth2 == foundIn) {
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moveChained({ neededBy, i, foundIn }, neededByDepth2 == foundIn);
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continue;
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}
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// Since we only have 4 items, this is as deep as the chain could go.
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int neededByDepth3 = findIndex(goal, state[neededByDepth2], i + 1);
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moveChained({ neededByDepth2, neededBy, i, foundIn }, neededByDepth3 == foundIn);
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}
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} else {
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fpr.Map4DirtyIn(inst.dest, inst.src1);
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for (int i = 0; i < 4; ++i) {
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int lane = (inst.src2 >> (i * 2)) & 3;
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FMV(32, fpr.R(inst.dest + i), fpr.R(inst.src1 + lane));
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}
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}
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break;
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case IROp::Vec4Blend:
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fpr.Map4DirtyInIn(inst.dest, inst.src1, inst.src2);
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for (int i = 0; i < 4; ++i) {
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int which = (inst.constant >> i) & 1;
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FMV(32, fpr.R(inst.dest + i), fpr.R((which ? inst.src2 : inst.src1) + i));
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}
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break;
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case IROp::Vec4Mov:
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fpr.Map4DirtyIn(inst.dest, inst.src1);
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for (int i = 0; i < 4; ++i)
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FMV(32, fpr.R(inst.dest + i), fpr.R(inst.src1 + i));
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void RiscVJitBackend::CompIR_VecArith(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Vec4Add:
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fpr.Map4DirtyInIn(inst.dest, inst.src1, inst.src2);
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for (int i = 0; i < 4; ++i)
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FADD(32, fpr.R(inst.dest + i), fpr.R(inst.src1 + i), fpr.R(inst.src2 + i));
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break;
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case IROp::Vec4Sub:
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fpr.Map4DirtyInIn(inst.dest, inst.src1, inst.src2);
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for (int i = 0; i < 4; ++i)
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FSUB(32, fpr.R(inst.dest + i), fpr.R(inst.src1 + i), fpr.R(inst.src2 + i));
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break;
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case IROp::Vec4Mul:
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fpr.Map4DirtyInIn(inst.dest, inst.src1, inst.src2);
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for (int i = 0; i < 4; ++i)
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FMUL(32, fpr.R(inst.dest + i), fpr.R(inst.src1 + i), fpr.R(inst.src2 + i));
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break;
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case IROp::Vec4Div:
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fpr.Map4DirtyInIn(inst.dest, inst.src1, inst.src2);
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for (int i = 0; i < 4; ++i)
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FDIV(32, fpr.R(inst.dest + i), fpr.R(inst.src1 + i), fpr.R(inst.src2 + i));
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break;
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case IROp::Vec4Scale:
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fpr.SpillLock(inst.src2);
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fpr.MapReg(inst.src2);
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fpr.Map4DirtyIn(inst.dest, inst.src1);
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fpr.ReleaseSpillLock(inst.src2);
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for (int i = 0; i < 4; ++i)
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FMUL(32, fpr.R(inst.dest + i), fpr.R(inst.src1 + i), fpr.R(inst.src2));
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break;
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case IROp::Vec4Neg:
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fpr.Map4DirtyIn(inst.dest, inst.src1);
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for (int i = 0; i < 4; ++i)
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FNEG(32, fpr.R(inst.dest + i), fpr.R(inst.src1 + i));
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break;
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case IROp::Vec4Abs:
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fpr.Map4DirtyIn(inst.dest, inst.src1);
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for (int i = 0; i < 4; ++i)
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FABS(32, fpr.R(inst.dest + i), fpr.R(inst.src1 + i));
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void RiscVJitBackend::CompIR_VecHoriz(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Vec4Dot:
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// TODO: Maybe some option to call the slow accurate mode?
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fpr.SpillLock(inst.dest);
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for (int i = 0; i < 4; ++i) {
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fpr.SpillLock(inst.src1 + i);
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fpr.SpillLock(inst.src2 + i);
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}
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for (int i = 0; i < 4; ++i) {
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fpr.MapReg(inst.src1 + i);
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fpr.MapReg(inst.src2 + i);
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}
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fpr.MapReg(inst.dest, MIPSMap::NOINIT);
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for (int i = 0; i < 4; ++i) {
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fpr.ReleaseSpillLock(inst.src1 + i);
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fpr.ReleaseSpillLock(inst.src2 + i);
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}
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fpr.ReleaseSpillLock(inst.dest);
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if ((inst.dest < inst.src1 + 4 && inst.dest >= inst.src1) || (inst.dest < inst.src2 + 4 && inst.dest >= inst.src2)) {
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// This means inst.dest overlaps one of src1 or src2. We have to do that one first.
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// Technically this may impact -0.0 and such, but dots accurately need to be aligned anyway.
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for (int i = 0; i < 4; ++i) {
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if (inst.dest == inst.src1 + i || inst.dest == inst.src2 + i)
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FMUL(32, fpr.R(inst.dest), fpr.R(inst.src1 + i), fpr.R(inst.src2 + i));
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}
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for (int i = 0; i < 4; ++i) {
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if (inst.dest != inst.src1 + i && inst.dest != inst.src2 + i)
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FMADD(32, fpr.R(inst.dest), fpr.R(inst.src1 + i), fpr.R(inst.src2 + i), fpr.R(inst.dest));
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}
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} else {
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FMUL(32, fpr.R(inst.dest), fpr.R(inst.src1), fpr.R(inst.src2));
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for (int i = 1; i < 4; ++i)
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FMADD(32, fpr.R(inst.dest), fpr.R(inst.src1 + i), fpr.R(inst.src2 + i), fpr.R(inst.dest));
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}
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void RiscVJitBackend::CompIR_VecPack(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Vec2Unpack16To31:
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case IROp::Vec2Unpack16To32:
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case IROp::Vec4Unpack8To32:
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case IROp::Vec4DuplicateUpperBitsAndShift1:
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case IROp::Vec4Pack31To8:
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case IROp::Vec4Pack32To8:
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case IROp::Vec2Pack31To16:
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CompIR_Generic(inst);
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break;
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case IROp::Vec2Pack32To16:
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fpr.MapDirtyInIn(inst.dest, inst.src1, inst.src1 + 1);
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FMV(FMv::X, FMv::W, SCRATCH1, fpr.R(inst.src1));
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FMV(FMv::X, FMv::W, SCRATCH2, fpr.R(inst.src1 + 1));
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// Keep in mind, this was sign-extended, so we have to zero the upper.
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SLLI(SCRATCH1, SCRATCH1, XLEN - 32);
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// Now we just set (SCRATCH2 & 0xFFFF0000) | SCRATCH1.
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SRLI(SCRATCH1, SCRATCH1, XLEN - 16);
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// Use a wall to mask. We can ignore the upper 32 here.
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SRLI(SCRATCH2, SCRATCH2, 16);
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SLLI(SCRATCH2, SCRATCH2, 16);
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OR(SCRATCH1, SCRATCH1, SCRATCH2);
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// Okay, to the floating point register.
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FMV(FMv::W, FMv::X, fpr.R(inst.dest), SCRATCH1);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void RiscVJitBackend::CompIR_VecClamp(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Vec4ClampToZero:
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case IROp::Vec2ClampToZero:
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CompIR_Generic(inst);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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} // namespace MIPSComp
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