Commit graph

12227 commits

Author SHA1 Message Date
Unknown W. Brackets
c24e3ef831 riscv: Implement ll/sc. 2023-07-30 00:45:51 -07:00
Unknown W. Brackets
26a527bdf8 riscv: Implement float/int conversion. 2023-07-30 00:45:51 -07:00
Henrik Rydgård
b93275bb35
Merge pull request #17800 from unknownbrackets/riscv-jit
More RISC-V jit ops
2023-07-30 09:26:22 +02:00
Henrik Rydgård
c8447ff4b7
Merge pull request #17801 from unknownbrackets/irjit-vminmax
irjit: Fix vmin/vmax nan handling
2023-07-30 09:18:25 +02:00
Henrik Rydgård
180bda6f6b
Merge pull request #17799 from unknownbrackets/irjit-lsu
Add ll/sc to IR and x86jit
2023-07-30 09:15:55 +02:00
Unknown W. Brackets
0036f3c494 riscv: Implement FMin/FMax. 2023-07-30 00:02:10 -07:00
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8e8081c686 riscv: Implement VFPU compares. 2023-07-30 00:02:10 -07:00
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9c9330a207 riscv: Implement float conditional move. 2023-07-30 00:02:10 -07:00
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70ff18a463 riscv: Implement count leading zeros. 2023-07-30 00:02:10 -07:00
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a5671bc716 riscv: Add simple debug log of missed ops. 2023-07-30 00:02:10 -07:00
Unknown W. Brackets
6aa4b0c5e1 irjit: Fix vmin/vmax nan handling.
Should be relevant to NFS MW and possibly other game bugs.
2023-07-29 19:13:12 -07:00
Unknown W. Brackets
6d4fb949c2 riscv: Implement float compare ops. 2023-07-29 19:02:15 -07:00
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6b632a103d riscv: Implement FSin/similar. 2023-07-29 19:02:15 -07:00
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921bd2391c riscv: Implement vi2s. 2023-07-29 19:02:15 -07:00
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e2765db4dc riscv: Implement division. 2023-07-29 19:02:15 -07:00
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f65b6fdb20 riscv: Remove incomplete block check.
It shouldn't be necessary and bad things would happen anyway if it did.
2023-07-29 19:02:15 -07:00
Unknown W. Brackets
8d60c10a64 riscv: Use jit address offsets directly.
We'll have IR able to use block number or target offset.
2023-07-29 19:02:15 -07:00
Unknown W. Brackets
b6d2e64aca Debugger: Fix disasm of ll/sc. 2023-07-29 18:50:09 -07:00
Unknown W. Brackets
9a8ac1fe08 x86jit: Implement ll/sc.
The point here is that breakpoints now work for ll and sc.
2023-07-29 18:49:45 -07:00
Unknown W. Brackets
e228748449 irjit: Add FCvtScaledSW to safely scale vi2f. 2023-07-29 18:30:15 -07:00
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a5a2671af3 irjit: Implement vf2ix.
Used in LittleBigPlanet when playing intro movies.
2023-07-29 18:01:08 -07:00
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f0d4267c5e HLE: Reset ll/sc link on any syscall.
This seems to happen from any syscall, which makes sense.
The bit isn't cleared on an sc, but a thread switch doesn't need to occur.
2023-07-29 17:57:56 -07:00
Unknown W. Brackets
df2462b1d9 irjit: Implement ll/sc.
These occur more than I expected in LittleBigPlanet while loading.
2023-07-29 17:57:44 -07:00
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48586ed0ad irjit: Combine Load32Left/Right even on unaligned.
This helps on devices that don't allow unaligned load/store.
2023-07-29 17:57:25 -07:00
Henrik Rydgård
4aa2b1fcac
Merge pull request #17783 from unknownbrackets/riscv-jit
Implement float/vec operations in RISC-V jit
2023-07-28 08:38:19 +02:00
Unknown W. Brackets
a181f6d5b8 riscv: Add a comment for FMUL testing later. 2023-07-27 22:16:29 -07:00
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5122b0c78e riscv: Cleanup unnecessary fcr31 func.
Don't need this, we use DYNAMIC.
2023-07-25 20:33:56 -07:00
Unknown W. Brackets
0c9dce8ba8 riscv: Implement vec4 dot. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets
23e9dffc68 riscv: Implement vec4 shuffle and init. 2023-07-25 20:33:56 -07:00
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4e17c59cc2 riscv: Implement simple vec4 ops via floats. 2023-07-25 20:33:56 -07:00
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df313bd296 riscv: Fix rounding mode setting. 2023-07-25 20:33:56 -07:00
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9157d992ac jit-ir: Implement cfc1/ctc1.
This makes it so we can track rounding mode changes.
2023-07-25 20:33:56 -07:00
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ca7a520a19 riscv: Implement FMul. 2023-07-25 20:33:56 -07:00
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9a9b371856 riscv: Implement FSign using FCLASS. 2023-07-25 20:33:56 -07:00
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05360d5c7a riscv: Implement simplest float ops. 2023-07-25 20:33:56 -07:00
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bb6fdd0246 riscv: Add floating point load/stores. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets
7071884a47 riscv: Handle rounding mode and ctrl transfers. 2023-07-25 20:33:56 -07:00
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067a033dc0 riscv: Add FPU regcache. 2023-07-25 20:33:56 -07:00
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c3db3d5187 arm64jit: When rouding unset, use nearest.
The 0/default rounding mode is nearest, not toward zero.
We set hasSetRounding only when fcr31 has a non-zero rounding mode or
flush to zero set.
2023-07-25 20:30:05 -07:00
Unknown W. Brackets
a8edf5fa24 riscv: Reduce bloat in jit fallbacks. 2023-07-25 19:42:04 -07:00
Unknown W. Brackets
b97b7f3663 riscv: Make some regcache methods private. 2023-07-25 19:42:04 -07:00
Unknown W. Brackets
3383d5b93a
Merge pull request #17751 from unknownbrackets/riscv-jit
Initial RISC-V jit based on IR
2023-07-25 00:42:22 -07:00
Henrik Rydgård
a72c4aa383 Actually fix the race condition. Can't do any initialization step while waiting. 2023-07-24 12:08:15 +02:00
Henrik Rydgård
3ae520c35d RetroAchievements: Fix another race condition, improve logging.
Seems to help the frontend problem.
2023-07-24 12:00:16 +02:00
Unknown W. Brackets
b6f83ca969 riscv: Cleanup some pointerification flags. 2023-07-23 21:17:55 -07:00
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18c48681a8 riscv: Implement multiply instructions. 2023-07-23 18:01:50 -07:00
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7f4689e8fa riscv: Use direct SLI/SLIU instructions.
Derp, I forgot these existed on RISC-V for a moment.
2023-07-23 18:01:46 -07:00
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ca15fa7061 riscv: Enable jit by default. 2023-07-23 18:01:00 -07:00
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4100767b5e riscv: Optimize SetConst a bit. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets
f7f7531500 riscv: Fix min/max normalization. 2023-07-23 18:01:00 -07:00