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37810 commits 81 branches 122 tags 700 MiB
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12353 commits

Author SHA1 Message Date
Henrik Rydgård
1cf2a161a0 Replace the notifications with a bare-bones progress bar 2023-08-17 14:42:25 +02:00
sum2012
e00a41702c Add GamedataInstall of osm 
fix #14688
 2023-08-17 14:22:30 +02:00
Henrik Rydgård
ef2d7a810a Add comments, move some stuff around, get rid of some indentation. No functionality change. 2023-08-15 18:34:06 +02:00
Henrik Rydgård
b9b7342ffd
Merge pull request #17350 from basharast/master 
UWP Improvements
 2023-08-14 15:54:04 +02:00
Henrik Rydgård
d1b6aa7faa SoftGPU headless crashfix 2023-08-14 11:23:28 +02:00
Henrik Rydgård
1b2cffe632 Address feedback 2023-08-14 11:06:20 +02:00
Henrik Rydgård
aadb700505 Fix turning off VSync on Android, logic fix 2023-08-14 11:02:29 +02:00
Henrik Rydgård
ff6e118fff Get rid of a lot of ifdefs around presentation mode. Instead, set things dynamically. 2023-08-14 11:02:29 +02:00
Henrik Rydgård
bec9c5611e Rename PresentationMode to PresentMode 2023-08-14 11:02:29 +02:00
Henrik Rydgård
1beb01af6a
Merge pull request #17905 from unknownbrackets/irjit-opt 
irjit: Implement some missing, handle partial Vec4s more
 2023-08-14 07:49:45 +02:00
Henrik Rydgård
63b3b31feb
Merge pull request #17906 from unknownbrackets/riscv-blocklink 
riscv: Fix crash on clear icache
 2023-08-14 07:42:38 +02:00
Henrik Rydgård
a7bc70834c
Merge pull request #17907 from unknownbrackets/riscv-minor 
riscv: Implement vs2i
 2023-08-14 07:41:45 +02:00
Unknown W. Brackets
52cc38bf2a riscv: Implement vs2i. 2023-08-13 18:27:19 -07:00
Unknown W. Brackets
3f8f8d36d9 riscv: Fix crash on clear icache. 
Oops, can't avoid marking all blocks invalid.  Luckily a syscall should
always take more bytes than the bail invalidated block code.
 2023-08-13 18:25:46 -07:00
Unknown W. Brackets
159b41a0fa irjit: Fuse unaligned svl.q/svr.q together. 
They're almost never used outside paired, which we can do on most
platforms easily.
 2023-08-13 18:10:40 -07:00
Unknown W. Brackets
5729de90d2 irjit: Use more partial Vec4s / Vec4Blend. 2023-08-13 18:10:40 -07:00
Unknown W. Brackets
2e6dbab5fa irjit: Add flag to prefer Vec4, use for add/sub. 
This will improve things when using SIMD.
 2023-08-13 18:10:40 -07:00
Unknown W. Brackets
e0be6858b8 irjit: Implement vcrs.t. 
As used in Jeanne d'Arc.
 2023-08-13 18:10:12 -07:00
Unknown W. Brackets
217a1837ed irjit: Allow typical prefixes in vdiv/vasin/etc. 
Some of these behave strangely, but there are some common usages that work
fine.
 2023-08-13 18:10:07 -07:00
Bashar Astifan
07c119a80c Merge branch 'master' of https://github.com/hrydgard/ppsspp 2023-08-14 02:45:28 +04:00
Unknown W. Brackets
87668a5720
Merge pull request #17902 from hrydgard/ui-bugfixes 
Some debug overlays don't make sense when not in-game, disable them
 2023-08-13 13:13:16 -07:00
Henrik Rydgård
dc4de340b3 Some debug overlays don't make sense when not in-game, disable them. Minor feedback fixes. 2023-08-13 21:54:24 +02:00
Henrik Rydgård
5a9a2bf6fe
Merge pull request #17779 from EmulatorJS/master 
Cleanup emscripten libretro target
 2023-08-13 21:40:24 +02:00
Henrik Rydgård
2cdcc413b7
Merge pull request #17898 from unknownbrackets/irjit-vfputemps 
irjit: Cleanup/purge FPU/VFPU temps
 2023-08-13 21:08:00 +02:00
Henrik Rydgård
5dcd14b17a
Merge pull request #17901 from unknownbrackets/riscv-disasm 
riscv: Add debug log of block disasm
 2023-08-13 21:07:37 +02:00
Unknown W. Brackets
f03cd0b2ad
Merge pull request #17899 from unknownbrackets/riscv-minor 
Minor RISC-V cleanups, frame profiler fix
 2023-08-13 11:19:42 -07:00
Henrik Rydgård
d6cdb6e5d9
Merge pull request #17900 from unknownbrackets/irjit-vsgelt 
irjit: Implement vsge/vslt
 2023-08-13 19:59:14 +02:00
Unknown W. Brackets
23c79f8e7f irjit: Implement vsge/vslt. 
These are not ideal especially for SIMD, but they do work.
Improves performance in Silent Hill on RISC-V by like 20%.
 2023-08-13 10:40:47 -07:00
Unknown W. Brackets
5d20f2aabd irjit: Simplify VecDo3. 2023-08-13 10:40:47 -07:00
Unknown W. Brackets
2b36e0a625 irjit: ZeroFpCond -> FpCondFromReg. 
We already have a zero reg, so this is more useful and symmetrical.
 2023-08-13 10:40:47 -07:00
Unknown W. Brackets
2bb67db43c riscv: Switch to the logBlocks model for disasm. 2023-08-13 10:37:21 -07:00
Unknown W. Brackets
8c036a889d riscv: Add debug log of block disasm. 2023-08-13 10:32:04 -07:00
Unknown W. Brackets
7cc6c5fa62 riscv: Fix load error w/o pointerify. 2023-08-13 10:20:28 -07:00
Unknown W. Brackets
be938a850b riscv: Remove FMul safety check. 
Let's just see if everything's right, this bloats multiplies a lot.
Doesn't seem to impact perf a lot, though.
 2023-08-13 10:20:20 -07:00
Unknown W. Brackets
fa53b80574 irjit: Cleanup/purge FPU/VFPU temps. 
A lot of cases are followed by an FMov that just moved the temp to a
regular register, from VFPU instructions playing safe about overlaps.
 2023-08-13 10:14:10 -07:00
Henrik Rydgård
7bb1914fd3 Add FrameTiming.cpp/h (with no real contents) 2023-08-13 17:57:43 +02:00
Henrik Rydgård
2a74a0b98a
Merge pull request #17893 from unknownbrackets/riscv-blocklink 
riscv: Enable block linking
 2023-08-13 12:40:39 +02:00
Ethan O'Brien
8426b35a80 Cleanup emscripten libretro build target 2023-08-12 14:38:35 -05:00
Unknown W. Brackets
81f67c717c riscv: Fix block link for prev blocks. 
Oops, was just reversed so never linking.
 2023-08-12 10:48:39 -07:00
Unknown W. Brackets
fcc90095f7 riscv: Enable block linking. 2023-08-12 09:37:02 -07:00
Unknown W. Brackets
247788806a irjit: Add direct helper for start PC. 
It's annoying always fetching length too.
 2023-08-12 09:37:02 -07:00
Unknown W. Brackets
b3cdf06c5a riscv: Write fixup on block invalidation. 2023-08-12 09:37:02 -07:00
Unknown W. Brackets
3757ebca2d irjit: Invalidate/finalize target blocks. 
Doesn't actually do anything yet, but adds plumbing.
 2023-08-12 09:37:02 -07:00
Henrik Rydgård
1ea11c233c Remove "SwapBuffers" from the GraphicsContext interface. 
Buildfixes

More buildfix

headless buildfix

One more buildfix
 2023-08-11 01:57:02 +02:00
Henrik Rydgård
7c60022979 Fix hang after exiting a game. After running a game, coreState is POWERDOWN which counts as stepping. 2023-08-10 23:52:24 +02:00
Henrik Rydgård
779a156251 PortManager warning fix. The #pragma pack stuff was redundant anyway 2023-08-10 17:15:57 +02:00
Henrik Rydgård
4b0ac494d0 Even more simplification 2023-08-10 17:15:57 +02:00
Henrik Rydgård
0477ba8c78 Core.cpp: Some slight simplifications 2023-08-10 17:15:56 +02:00
Henrik Rydgård
be708e3e02 Move KeepScreenAwake to platform specific code. 2023-08-10 16:12:12 +02:00
Henrik Rydgård
50ea506b6a Revert "Regression experiment: Temporarily revert to returning 0 from bad achievement memory accesses." 
This reverts commit a044d8ccc2.
 2023-08-09 16:16:39 +02:00