Emulation/ppsspp
1
0
Fork 0
mirror of https://github.com/hrydgard/ppsspp.git synced 2025-04-02 11:01:50 -04:00
Code Issues Projects Releases Packages Wiki Activity

x86jit: Optimize simd->non for 1-lane a little.

Browse source
This commit is contained in:
Unknown W. Brackets 2014-11-26 09:20:50 -08:00
parent 5d0c32d1e6
commit e5dabaabe2
1 changed files with 6 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
Core/MIPS/x86/RegCacheFPU.cpp
View file

@ -420,8 +420,12 @@ void FPURegCache::SimpleRegsV(const u8 *v, MatrixSize msz, int flags) {
}
void FPURegCache::SimpleRegV(const u8 v, int flags) {
const MIPSCachedFPReg &vr = vregs[v];
if (vr.lane != 0) {
MIPSCachedFPReg &vr = vregs[v];
// Special optimization: if it's in a single simd, we can keep it there.
if (vr.lane == 1 && xregs[VSX(v)].mipsRegs[1] == -1) {
// Just change the lane to 0.
vr.lane = 0;
} else if (vr.lane != 0) {
// This will never end up in a register this way, so ignore dirty.
if ((flags & MAP_NOINIT)) {
// This will discard only this reg, and store the others.