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48 commits

Author SHA1 Message Date
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b9de1a44df jit: Reduce some include pollution. 
Usually no need for all of MIPSAnalyst.
 2022-10-27 23:26:44 -07:00
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4178f09e57 Build: More consistently avoid _M_ defines. 
We use PPSSPP_ARCH in several places already, this makes it more complete.
 2021-03-02 21:49:21 -08:00
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cae0815095 jit: Avoid using mips identifier directly. 
Apparently this gets defined on mips systems.
 2021-02-26 07:24:58 -08:00
Henrik Rydgård
0829543987 Third part of getting rid of PanicAlert 2020-07-19 20:34:02 +02:00
Henrik Rydgård
c5e0b799d9 Remove category from _assert_msg_ functions. We don't filter these by category anyway. 
Fixes the inconsistency where we _assert_ didn't take a category but
_assert_msg_ did.
 2020-07-19 20:33:25 +02:00
Henrik Rydgård
31de5a5082 Improve an assert message that AkiraJkr saw. Fix a silly bug in the last commit. 2019-08-23 18:42:10 +02:00
Henrik Rydgård
567937fa4d x64: Enable non-RIP addressing for FPU registers 2017-07-07 11:33:07 +02:00
Henrik Rydgård
7c1ae5b3e6 Move tempValues into MIPSState 2017-07-07 11:33:05 +02:00
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e65e794f28 x86jit: Fix vmmul of matrix with itself. 
Was not SIMDing correctly.  Probably rare in practice.
 2016-05-21 23:02:29 -07:00
Henrik Rydgård
c1b91ff5c1 x86: Add a way to eliminate some mov instructions. 
Not currently used yet.
 2015-04-12 13:50:23 -07:00
Chin
37f50a3792 Change to pass some arguments by reference 2015-03-01 16:49:00 +01:00
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9dd6bb56bb jit: Make available js_ and jo_ in regcaches. 2014-12-07 21:07:23 -08:00
Henrik Rydgard
51d55bd645 Namespacing cleanup (it's bad to do "using namespace" in a header) 2014-12-07 14:44:15 +01:00
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c6b090d82e x86jit: When storing, verify alignment. 2014-11-30 13:06:16 -08:00
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0000be1bb2 x86jit: Add a MAP_NOLOCK flag to not lock. 
Only for MapRegs*.  And then lock all by default, including
TryMapRegsVS().
 2014-11-30 10:36:44 -08:00
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bb26e4f7d0 x86jit: Implement vmmov using SIMD. 
4x -> 87x in microbenchmarking.
 2014-11-29 18:46:38 -08:00
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f6f943de63 jit: MAP_NOINIT should always mean MAP_DIRTY. 2014-11-29 00:14:08 -08:00
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bbeb5758b7 x86jit: Simplify VS() / VSX() usage. 2014-11-27 00:07:17 -08:00
Henrik Rydgard
b3c8a82c49 x86 jit: SIMD-ify some more 2014-11-25 23:56:46 +01:00
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ab7dd0df25 x86jit: Add an option to enable/disable vpfu simd. 2014-11-17 20:37:27 -08:00
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ed501302a2 x86jit: Add a check to see if we can map simd. 2014-11-16 15:05:16 -08:00
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27148d3712 x86jit: Add some helpers to check state. 2014-11-16 13:33:16 -08:00
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de566be2ce x86jit: Split out the logic for loading simd regs. 2014-11-16 13:33:15 -08:00
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aad505e7b3 x86jit: Add a TryMapDirtyInInVS() for 3-op. 2014-11-16 13:33:14 -08:00
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88a753eff3 x86jit: Add an invariant contract to the fpu cache. 
This should help catch things better in debug mode.
 2014-11-16 13:33:14 -08:00
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39afeb490f x86jit: Add some typesafety. 2014-11-16 13:33:13 -08:00
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4335bf3346 x86jit: Add basic mapping of SIMD regs. 
Not tested yet, just sketched out.  All very suboptimal.
 2014-11-16 13:33:13 -08:00
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9429359b47 x86jit: Add fallbacks when moving from VS -> V. 2014-11-16 13:33:12 -08:00
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4cf0913692 x86jit: Sketch some initial SIMD apis. 2014-11-16 13:33:07 -08:00
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3001866d18 Skip flushing FPU/VFPU regs if none were allocated. 
They're not used as often, so this usually saves time.  About 1% during
tests.
 2014-03-30 00:42:25 -07:00
Henrik Rydgard
55500d4bb6 Reorder VFPU registers in memory so that we can flush and reload them in bulk more often. 
Doesn't actually do that yet, that's for the NEON branch.
 2013-11-28 13:27:51 +01:00
Sacha
95881bdaac Blackberry: Add simulator support. 2013-11-26 12:18:34 +10:00
Henrik Rydgard
5ad04a23f4 x86 jit: Rename BindToRegister to MapReg 2013-11-09 15:23:31 +01:00
Henrik Rydgård
07a868910e Add a temporary hack option that may help debugging the wipeout glow. 
It reduces the glow problem by a lot but is obviously incorrect.
 2013-10-30 22:47:36 +01:00
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e8091dce44 Speed up FPURegCache::Start() on x86. 
This cuts that func by 97% when running the automated tests, and it was 8%
of the total time.  Won't really affect games.
 2013-10-24 08:27:42 -07:00
Henrik Rydgard
e08ac100ce Update native with workaround for #4078 and add some comments 2013-10-08 20:11:01 +02:00
Henrik Rydgard
7ca6d73857 Two approaches to vh2f (half-float to float): lookuptable and fast SSE 2013-09-28 22:08:44 +02:00
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64c2ea86c0 Add a method to save the gpr/fpr state in jit. 2013-08-16 00:12:49 -07:00
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0bfc380575 Try to reuse temp regs for better caching. 2013-02-18 00:32:42 -08:00
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18c03d0816 Handle temp regs better, no need for direct access. 2013-02-18 00:11:57 -08:00
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08a42a1aaf Preserve orig regs when applying vfpu prefixes. 2013-02-17 22:37:56 -08:00
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d63548799b Add more temp regs, allow swapping if necessary. 2013-02-17 22:18:46 -08:00
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6eae8ed36a Disable VDot and Vec3 in x86 jit, broke things. 2013-02-16 19:57:35 -08:00
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0bd382c518 Discard temp regs right away, some helper funcs. 2013-02-16 10:18:13 -08:00
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35537b3c97 Add TEMP0 fpu regs to x86 like in armjit. 
But... will probably need more and the ability to swap into memory
if we want to deal with prefixes.
 2013-02-16 03:27:03 -08:00
Henrik Rydgard
78923f5538 Jit a little more (vfpu single load/store, transfer instructions) 2013-02-10 12:14:55 +01:00
Henrik Rydgard
2738417040 VFPU JIT: start setting up infrastructure. very incomplete. vdot works if undisabled, but isn't complete. 2013-01-26 01:34:19 +01:00
Henrik Rydgard
68991511ee Split out the FPU reg cache into its own file too. 2013-01-26 01:34:19 +01:00