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Handle temp regs better, no need for direct access.

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Unknown W. Brackets 2013-02-17 23:14:22 -08:00
parent 27942606ad
commit 18c03d0816
2 changed files with 10 additions and 14 deletions
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5
Core/MIPS/x86/RegCacheFPU.cpp
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@ -27,6 +27,7 @@ FPURegCache::FPURegCache() : emit(0), mips(0) {
memset(regs, 0, sizeof(regs));
memset(xregs, 0, sizeof(xregs));
vregs = regs + 32;
tempRoundRobin = 0;
}
void FPURegCache::Start(MIPSState *mips, MIPSAnalyst::AnalysisResults &stats) {
@ -153,7 +154,9 @@ bool FPURegCache::IsTempX(X64Reg xr) {
}
int FPURegCache::GetTempR() {
for (int r = TEMP0; r < TEMP0 + NUM_TEMPS; ++r) {
for (int i = 0; i < NUM_TEMPS; ++i) {
// Make sure we don't give out the same one over and over, even if not locked.
int r = TEMP0 + (tempRoundRobin++ + i) % NUM_TEMPS;
if (!regs[r].away) {
return r;
}

19
Core/MIPS/x86/RegCacheFPU.h
View file

@ -27,22 +27,14 @@ using namespace Gen;
// GPRs are numbered 0 to 31
// VFPU regs are numbered 32 to 159.
// Then we have some temp regs for VFPU handling from 160 to 171.
// Then we have some temp regs for VFPU handling from 160 to 175.
// Temp regs: 4 from S prefix, 4 from T prefix, 4 from D mask, and 4 for work (worst case.)
// But most of the time prefixes aren't used that heavily so we won't use all of them.
enum {
NUM_TEMPS = 12,
NUM_TEMPS = 16,
TEMP0 = 32 + 128,
TEMP1 = TEMP0 + 1,
TEMP2 = TEMP0 + 2,
TEMP3 = TEMP0 + 3,
TEMP4 = TEMP0 + 4,
TEMP5 = TEMP0 + 5,
TEMP6 = TEMP0 + 6,
TEMP7 = TEMP0 + 7,
TEMP8 = TEMP0 + 8,
TEMP9 = TEMP0 + 9,
TEMP10 = TEMP0 + 10,
TEMP11 = TEMP0 + 11,
NUM_MIPS_FPRS = 32 + 128 + NUM_TEMPS,
};
@ -148,6 +140,7 @@ private:
// TEMP0, etc. are swapped in here if necessary (e.g. on x86.)
static u32 tempValues[NUM_TEMPS];
int tempRoundRobin;
XEmitter *emit;
};