Herman Semenov
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4ea842a3c1
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Minor replaced insert to emplace C++11
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2023-12-19 16:06:48 +03:00 |
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Unknown W. Brackets
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9b2fa46861
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IR: Add mini native jit MIPS block profiler.
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2023-09-24 23:04:29 -07:00 |
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Henrik Rydgård
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06a1f0b72c
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Merge pull request #18226 from unknownbrackets/x86-ir-breakpoints
x86jit: Improve memory breakpoint speed
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2023-09-25 00:47:22 +02:00 |
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Unknown W. Brackets
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e433a8be4a
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arm64jit: Speed up memchecks, add validation.
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2023-09-24 07:42:11 -07:00 |
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Unknown W. Brackets
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34ff24a4f3
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irjit: Describe native offsets better.
Also check in case of non-linear blocks, can happen with preload.
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2023-09-24 07:05:30 -07:00 |
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Unknown W. Brackets
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1b756ff8c1
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arm64jit: Add initial base for IR jit.
This works, but very slowly at this point.
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2023-09-03 12:14:28 -07:00 |
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Unknown W. Brackets
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2e64abd2a0
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x86jit: Improve some debug labels.
Helps when running a profiler that reads these.
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2023-08-27 12:51:29 -07:00 |
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Unknown W. Brackets
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3f8f8d36d9
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riscv: Fix crash on clear icache.
Oops, can't avoid marking all blocks invalid. Luckily a syscall should
always take more bytes than the bail invalidated block code.
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2023-08-13 18:25:46 -07:00 |
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Henrik Rydgård
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d6cdb6e5d9
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Merge pull request #17900 from unknownbrackets/irjit-vsgelt
irjit: Implement vsge/vslt
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2023-08-13 19:59:14 +02:00 |
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Unknown W. Brackets
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2b36e0a625
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irjit: ZeroFpCond -> FpCondFromReg.
We already have a zero reg, so this is more useful and symmetrical.
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2023-08-13 10:40:47 -07:00 |
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Unknown W. Brackets
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81f67c717c
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riscv: Fix block link for prev blocks.
Oops, was just reversed so never linking.
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2023-08-12 10:48:39 -07:00 |
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Unknown W. Brackets
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fcc90095f7
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riscv: Enable block linking.
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2023-08-12 09:37:02 -07:00 |
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Unknown W. Brackets
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b3cdf06c5a
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riscv: Write fixup on block invalidation.
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2023-08-12 09:37:02 -07:00 |
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Unknown W. Brackets
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3757ebca2d
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irjit: Invalidate/finalize target blocks.
Doesn't actually do anything yet, but adds plumbing.
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2023-08-12 09:37:02 -07:00 |
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Unknown W. Brackets
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ad4cbbab8e
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riscv: Don't cache mipState on backend.
Bad sign if we're trying to use it, anyway.
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2023-08-08 23:17:32 -07:00 |
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Unknown W. Brackets
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79ca880ac7
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irjit: Implement vqmul, add Vec4Blend.
Should be useful more places.
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2023-08-06 13:38:00 -07:00 |
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Unknown W. Brackets
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93e3d35f5d
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irjit: Move more to IRNativeBackend, split.
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2023-08-06 00:16:43 -07:00 |
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Unknown W. Brackets
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691799a0ca
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irjit: Centralize native jit compile dispatch.
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2023-08-03 23:14:58 -07:00 |
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