Emulation/ppsspp
1
0
Fork 0
mirror of https://github.com/hrydgard/ppsspp.git synced 2025-04-02 11:01:50 -04:00
Code Issues Projects Releases Packages Wiki Activity
40100 commits 81 branches 122 tags 700 MiB
Commit graph

67 commits

Author SHA1 Message Date
Herman Semenov
17ecee1715 Fixed return copies from functions and const ref params 2024-04-02 18:37:00 +03:00
Herman Semenov
b871e76d05 [Core/Debugger/FileLoaders/FileSystems/MIPS] Using reserve if possible 2023-12-15 13:59:19 +03:00
Unknown W. Brackets
57123e8f9e irjit: Reserve some arrays that churn. 
Improves IR compile time by around 20-30%.
 2023-08-20 08:59:47 -07:00
Unknown W. Brackets
159b41a0fa irjit: Fuse unaligned svl.q/svr.q together. 
They're almost never used outside paired, which we can do on most
platforms easily.
 2023-08-13 18:10:40 -07:00
Unknown W. Brackets
2e6dbab5fa irjit: Add flag to prefer Vec4, use for add/sub. 
This will improve things when using SIMD.
 2023-08-13 18:10:40 -07:00
Unknown W. Brackets
247788806a irjit: Add direct helper for start PC. 
It's annoying always fetching length too.
 2023-08-12 09:37:02 -07:00
Unknown W. Brackets
3757ebca2d irjit: Invalidate/finalize target blocks. 
Doesn't actually do anything yet, but adds plumbing.
 2023-08-12 09:37:02 -07:00
Unknown W. Brackets
f870271011 riscv: Spill registers more intelligently. 2023-07-30 14:24:12 -07:00
Unknown W. Brackets
8d60c10a64 riscv: Use jit address offsets directly. 
We'll have IR able to use block number or target offset.
 2023-07-29 19:02:15 -07:00
Unknown W. Brackets
3468423bb4 Debugger: Handle missing crash/block ptrs better. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets
e4f9c72fe9 riscv: Avoid unaligned mem combine in IR. 2023-07-16 16:20:58 -07:00
Unknown W. Brackets
d4e689b096 irjit: Allow IRInterpret() on partial block. 
For later if we want to fallback from native to IR interpret.
 2023-07-16 16:19:53 -07:00
Unknown W. Brackets
46101581c0 Core: Cleanup disasm buffer usage. 2023-04-29 09:07:25 -07:00
Unknown W. Brackets
80e481bbdc Core: Show exception on misaligned jump. 2022-08-21 14:49:34 -07:00
Unknown W. Brackets
25e18195ce irjit: Allow unaligned loads by default. 
This was the original intention, was a mistake that this was flipped.
 2022-07-11 17:36:39 -07:00
Unknown W. Brackets
2479d52202 Global: Reduce includes of common headers. 
In many places, string, map, or Common.h were included but not needed.
 2022-01-30 16:35:33 -08:00
Unknown W. Brackets
cae0815095 jit: Avoid using mips identifier directly. 
Apparently this gets defined on mips systems.
 2021-02-26 07:24:58 -08:00
Unknown W. Brackets
f32f89dd90 Global: Remove some unused variables. 2021-02-15 11:59:45 -08:00
Henrik Rydgård
821817e6d4 Move the profiler to Common 2020-10-04 11:42:16 +02:00
Unknown W. Brackets
53d9c10b22 irjit: Switch to XXH3. 2020-08-27 20:40:55 -07:00
Henrik Rydgård
b43698a13d Remove most instances of base/logging.h from Common, Core, GPU, more 2020-08-15 19:08:44 +02:00
Unknown W. Brackets
b8342fb8ec SaveState: Rename ChunkFile files to Serialize. 
Makes more sense and less weird than ChunkFileDoMap, etc.
 2020-08-10 08:04:05 +00:00
Unknown W. Brackets
1dc5ee424b SaveState: Split out Do types to reduce headers. 2020-08-10 08:03:44 +00:00
Henrik Rydgård
c5e0b799d9 Remove category from _assert_msg_ functions. We don't filter these by category anyway. 
Fixes the inconsistency where we _assert_ didn't take a category but
_assert_msg_ did.
 2020-07-19 20:33:25 +02:00
Unknown W. Brackets
3c34c7c456 irjit: Add jump crash checks. 
Doesn't seem to have any significant impact on performance.
 2020-07-12 22:17:36 -07:00
Unknown W. Brackets
46649a218e Core: Add flags to disable jit features. 
Not actually disabling yet, just setup.
 2019-02-03 13:58:24 -08:00
Unknown W. Brackets
09e307b097 arm64jit: Update rounding mode on thread switch. 
Since fcr31 is per-thread, we must update jit state when it changes.
This also fixes the rounding mode on load state and jit/interp switch.
 2018-04-01 10:12:32 -07:00
Unknown W. Brackets
97674b80bd irjit: Skip preloading blocks with jump to 0. 
These will be changed before executing anyway.
 2018-01-06 17:23:53 -08:00
Unknown W. Brackets
cc8e9a93c3 irjit: For debug, return the best block at addr. 
Invalidation may result in multiple matching blocks, prefer any that is
currently valid.
 2018-01-06 17:08:54 -08:00
Unknown W. Brackets
463b2a90c7 irjit: Allow precompiling funcs at start. 
This can take a second, but cuts down on jitc spikes throughout runtime.
Note: bits of the game will still be recompiled as games change code.

This is basically the same operation as loading from cache, without the
cache yet.
 2018-01-06 17:06:53 -08:00
Unknown W. Brackets
ccd562d934 irjit: Add a safety check for block num overflow. 
In case a game is very frequently modifying some block.
 2018-01-04 23:24:15 -08:00
Unknown W. Brackets
0bfab27b46 irjit: Calculate bloat statistics. 
At least based on IR for now.  Can do something else later.

memset() was causing a crash on the std::map.
 2018-01-04 23:09:03 -08:00
Henrik Rydgård
d1d01bfdcb Cleanup GetBlockNumberFromStartAddress 2018-01-05 01:20:10 +01:00
Henrik Rydgård
468b830bec Show IR disassembly in JIT Compare screen 2018-01-04 12:23:23 +01:00
Unknown W. Brackets
cffb2d61a7 irjit: Embed constant inside IRInst. 
This simplifies a bunch of code and improves compile performance by about
30%, at the cost of a bit more memory.
 2018-01-03 23:24:04 -08:00
Unknown W. Brackets
b37ba9e599 irjit: Add options for compile/optimize steps. 
This way the backend can set flags for the type of IR it wants.  It's
seems too complex to combine certain things like lwl/lwr in a pass.
 2018-01-01 08:38:12 -08:00
Unknown W. Brackets
8ffb0101fe jit: Report blocks with uneaten VFPU prefixes. 
There may be options to avoid, like continuing these blocks, especially if
they're likely or something.
 2018-01-01 08:38:10 -08:00
Unknown W. Brackets
3af78883c7 irjit: Speed up icache block invalidation. 
Turns out, in games using a ton of small memcpys, this was causing perf
issues.
 2017-12-31 10:37:09 -08:00
Henrik Rydgård
0207739d76 Can't call functions through known-nil pointers, even if they don't touch local data - LLVM's optimizer might have done something stupid. 2017-11-30 01:07:03 +01:00
Henrik Rydgård
635b2ada43 Remove a function that didn't make a lot of sense. 2017-01-26 09:50:16 +01:00
Unknown W. Brackets
e55198f7e7 Correct some initialization order warnings. 
Also, another missing init with IRBlocks.
 2016-08-05 10:46:11 -07:00
Unknown W. Brackets
1de4943632 jit-ir: Avoid crash in stack walk. 
This can happen if something is data, I suppose, and not a valid block.
 2016-07-02 20:51:06 -07:00
Unknown W. Brackets
1df08518ae jit-ir: Implement basic icache clear. 2016-07-01 17:27:24 -07:00
Unknown W. Brackets
6fb34d0bee jit-ir: Add initial breakpoint support. 
No memory breakpoints yet, and cache isn't cleared yet so these don't work
exactly the way you might expect...
 2016-07-01 17:15:57 -07:00
Unknown W. Brackets
6bf1390603 Fix timing drift on CoreTiming::ForceCheck(). 
Since -1 -(-1) = 0, we'll never think we moved forward this way.
 2016-05-15 12:43:34 -07:00
Unknown W. Brackets
e37777648e jit-ir: Restore emuhacks before saving state. 
Let's just ask jit to do this, not its block cache directly.
 2016-05-14 08:59:44 -07:00
Unknown W. Brackets
b74df87db0 jit-ir: Clear emuhacks on block destroy. 2016-05-14 08:40:53 -07:00
Henrik Rydgard
45efcda6b1 IR: Some more VFPU 2016-05-10 21:50:08 +02:00
Henrik Rydgard
28087a6088 IRFrontend shouldn't know about IRBlock 2016-05-09 20:18:22 +02:00
Henrik Rydgard
e711a47a75 Complete the separation of the IR compiler frontend from the "Jit" 2016-05-09 20:05:06 +02:00