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riscv: Avoid unaligned mem combine in IR.

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Unknown W. Brackets 2023-07-16 16:20:58 -07:00
parent d4e689b096
commit e4f9c72fe9
1 changed files with 4 additions and 0 deletions
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4
Core/MIPS/IR/IRJit.cpp
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@ -15,6 +15,7 @@
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "ppsspp_config.h"
#include <set>
#include "ext/xxhash.h"
@ -49,7 +50,10 @@ IRJit::IRJit(MIPSState *mipsState) : frontend_(mipsState->HasDefaultPrefix()), m
IROptions opts{};
opts.disableFlags = g_Config.uJitDisableFlags;
// Assume that RISC-V always has very slow unaligned memory accesses.
#if !PPSSPP_ARCH(RISCV64)
opts.unalignedLoadStore = (opts.disableFlags & (uint32_t)JitDisable::LSU_UNALIGNED) == 0;
#endif
frontend_.SetOptions(opts);
}