Emulation/ppsspp
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42256 commits 81 branches 122 tags 700 MiB
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25 commits

Author SHA1 Message Date
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8dfc2f04d7 riscv: Use a single reg for LO/HI. 
This is the same optimization we have for arm64, basically.
 2023-08-20 14:49:09 -07:00
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6a75e6712e riscv: Use automapping for special cases too. 2023-08-20 12:42:11 -07:00
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cc4bc406d5 riscv: Cleanup VfpuCtrlToReg meta, use auto-map. 2023-08-20 12:42:11 -07:00
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e40ae60029 riscv: Mark normalized32 after mapping. 
It's less confusing to separate it.
 2023-08-20 12:42:11 -07:00
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f9bf7de701 riscv: Use a single reg cache. 2023-08-20 12:42:11 -07:00
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a23ade8f75 riscv: Map IR regs based on metadata. 
Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
 2023-08-20 12:42:11 -07:00
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718a1b3944 riscv: Centralize MarkDirty flagging. 2023-08-19 16:15:49 -07:00
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4e41f83ecc riscv: Centralize IR reg cache metadata checks. 
These are all largely the same between backends.
 2023-08-17 23:03:31 -07:00
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0b4e7d60f9 riscv: Implement ReverseBits in jit. 2023-08-08 23:17:32 -07:00
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93e3d35f5d irjit: Move more to IRNativeBackend, split. 2023-08-06 00:16:43 -07:00
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e34736fbb2 riscv: Reduce norms in Slt/Sltu overlap cases. 
We can skip an SEXT.W in common cases where the dest and src overlap.
 2023-07-30 14:19:28 -07:00
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d1dc346899 riscv: Fix pointer add/sub. 2023-07-30 14:19:28 -07:00
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70ff18a463 riscv: Implement count leading zeros. 2023-07-30 00:02:10 -07:00
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e2765db4dc riscv: Implement division. 2023-07-29 19:02:15 -07:00
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18c48681a8 riscv: Implement multiply instructions. 2023-07-23 18:01:50 -07:00
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7f4689e8fa riscv: Use direct SLI/SLIU instructions. 
Derp, I forgot these existed on RISC-V for a moment.
 2023-07-23 18:01:46 -07:00
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f7f7531500 riscv: Fix min/max normalization. 2023-07-23 18:01:00 -07:00
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92694e765f riscv: Implement conditional moves. 2023-07-23 18:01:00 -07:00
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2c7da94bd1 riscv: Implement shifts and compares. 2023-07-23 18:01:00 -07:00
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5ed2f0d559 riscv: Implement logic ops. 2023-07-23 18:01:00 -07:00
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94be343591 riscv: Try to keep regs normalized, track. 
Since we can't address the lower 32-bits only in compares, this can help
us avoid renormalizing before a compare.
 2023-07-23 18:01:00 -07:00
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d31eded9ba riscv: Allow dirty pointers, explicitly. 2023-07-23 18:01:00 -07:00
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c2da7d18bb riscv: Stub out more IR compilation categories. 2023-07-23 18:01:00 -07:00
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05a2789cf4 riscv: Implement some simple assign instructions. 2023-07-23 18:01:00 -07:00
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bf7a6eb2cd riscv: Add jit for some initial instructions. 2023-07-23 18:01:00 -07:00