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riscv: Cleanup VfpuCtrlToReg meta, use auto-map.

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Unknown W. Brackets 2023-08-20 10:56:46 -07:00
parent e40ae60029
commit cc4bc406d5
5 changed files with 15 additions and 21 deletions
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2
Core/MIPS/IR/IRInst.cpp
View file

@ -117,7 +117,7 @@ static const IRMeta irMeta[] = {
{ IROp::FpCondToReg, "FpCondToReg", "G" },
{ IROp::FpCtrlFromReg, "FpCtrlFromReg", "_G" },
{ IROp::FpCtrlToReg, "FpCtrlToReg", "G" },
{ IROp::VfpuCtrlToReg, "VfpuCtrlToReg", "GI" },
{ IROp::VfpuCtrlToReg, "VfpuCtrlToReg", "GT" },
{ IROp::SetCtrlVFPU, "SetCtrlVFPU", "TC" },
{ IROp::SetCtrlVFPUReg, "SetCtrlVFPUReg", "TG" },
{ IROp::SetCtrlVFPUFReg, "SetCtrlVFPUFReg", "TF" },

8
Core/MIPS/RiscV/RiscVCompALU.cpp
View file

@ -646,7 +646,7 @@ void RiscVJitBackend::CompIR_Mult(IRInst inst) {
break;
case IROp::Madd:
regs_.MapGPRDirtyDirtyInIn(IRREG_LO, IRREG_HI, inst.src1, inst.src2, MapType::ALWAYS_LOAD);
regs_.MapGPRDirtyDirtyInIn(IRREG_LO, IRREG_HI, inst.src1, inst.src2, false);
NormalizeSrc12(inst, &lhs, &rhs, SCRATCH1, SCRATCH2, true);
MUL(SCRATCH1, lhs, rhs);
@ -656,7 +656,7 @@ void RiscVJitBackend::CompIR_Mult(IRInst inst) {
break;
case IROp::MaddU:
regs_.MapGPRDirtyDirtyInIn(IRREG_LO, IRREG_HI, inst.src1, inst.src2, MapType::ALWAYS_LOAD);
regs_.MapGPRDirtyDirtyInIn(IRREG_LO, IRREG_HI, inst.src1, inst.src2, false);
makeArgsUnsigned(&lhs, &rhs);
MUL(SCRATCH1, lhs, rhs);
@ -666,7 +666,7 @@ void RiscVJitBackend::CompIR_Mult(IRInst inst) {
break;
case IROp::Msub:
regs_.MapGPRDirtyDirtyInIn(IRREG_LO, IRREG_HI, inst.src1, inst.src2, MapType::ALWAYS_LOAD);
regs_.MapGPRDirtyDirtyInIn(IRREG_LO, IRREG_HI, inst.src1, inst.src2, false);
NormalizeSrc12(inst, &lhs, &rhs, SCRATCH1, SCRATCH2, true);
MUL(SCRATCH1, lhs, rhs);
@ -676,7 +676,7 @@ void RiscVJitBackend::CompIR_Mult(IRInst inst) {
break;
case IROp::MsubU:
regs_.MapGPRDirtyDirtyInIn(IRREG_LO, IRREG_HI, inst.src1, inst.src2, MapType::ALWAYS_LOAD);
regs_.MapGPRDirtyDirtyInIn(IRREG_LO, IRREG_HI, inst.src1, inst.src2, false);
makeArgsUnsigned(&lhs, &rhs);
MUL(SCRATCH1, lhs, rhs);

7
Core/MIPS/RiscV/RiscVCompSystem.cpp
View file

@ -94,14 +94,13 @@ void RiscVJitBackend::CompIR_Transfer(IRInst inst) {
break;
case IROp::SetCtrlVFPUReg:
regs_.MapGPRDirtyIn(IRREG_VFPU_CTRL_BASE + inst.dest, inst.src1);
regs_.Map(inst);
MV(regs_.R(IRREG_VFPU_CTRL_BASE + inst.dest), regs_.R(inst.src1));
regs_.MarkGPRDirty(IRREG_VFPU_CTRL_BASE + inst.dest, regs_.IsNormalized32(inst.src1));
break;
case IROp::SetCtrlVFPUFReg:
regs_.MapGPR(IRREG_VFPU_CTRL_BASE + inst.dest, MIPSMap::NOINIT);
regs_.MapFPR(inst.src1);
regs_.Map(inst);
FMV(FMv::X, FMv::W, regs_.R(IRREG_VFPU_CTRL_BASE + inst.dest), regs_.F(inst.src1));
regs_.MarkGPRDirty(IRREG_VFPU_CTRL_BASE + inst.dest, true);
break;
@ -154,7 +153,7 @@ void RiscVJitBackend::CompIR_Transfer(IRInst inst) {
break;
case IROp::VfpuCtrlToReg:
regs_.MapGPRDirtyIn(inst.dest, IRREG_VFPU_CTRL_BASE + inst.src1);
regs_.Map(inst);
MV(regs_.R(inst.dest), regs_.R(IRREG_VFPU_CTRL_BASE + inst.src1));
regs_.MarkGPRDirty(inst.dest, regs_.IsNormalized32(IRREG_VFPU_CTRL_BASE + inst.src1));
break;

10
Core/MIPS/RiscV/RiscVRegCache.cpp
View file

@ -255,18 +255,18 @@ RiscVReg RiscVRegCache::MapGPRAsPointer(IRReg reg) {
return (RiscVReg)MapNativeRegAsPointer(reg);
}
void RiscVRegCache::MapGPRDirtyIn(IRReg rd, IRReg rs, MapType type) {
void RiscVRegCache::MapGPRDirtyIn(IRReg rd, IRReg rs, bool avoidLoad) {
SpillLockGPR(rd, rs);
bool load = type == MapType::ALWAYS_LOAD || rd == rs;
bool load = !avoidLoad || rd == rs;
MapGPR(rd, load ? MIPSMap::DIRTY : MIPSMap::NOINIT);
MapGPR(rs);
ReleaseSpillLockGPR(rd, rs);
}
void RiscVRegCache::MapGPRDirtyDirtyInIn(IRReg rd1, IRReg rd2, IRReg rs, IRReg rt, MapType type) {
void RiscVRegCache::MapGPRDirtyDirtyInIn(IRReg rd1, IRReg rd2, IRReg rs, IRReg rt, bool avoidLoad) {
SpillLockGPR(rd1, rd2, rs, rt);
bool load1 = type == MapType::ALWAYS_LOAD || (rd1 == rs || rd1 == rt);
bool load2 = type == MapType::ALWAYS_LOAD || (rd2 == rs || rd2 == rt);
bool load1 = !avoidLoad || (rd1 == rs || rd1 == rt);
bool load2 = !avoidLoad || (rd2 == rs || rd2 == rt);
MapGPR(rd1, load1 ? MIPSMap::DIRTY : MIPSMap::NOINIT);
MapGPR(rd2, load2 ? MIPSMap::DIRTY : MIPSMap::NOINIT);
MapGPR(rt);

9
Core/MIPS/RiscV/RiscVRegCache.h
View file

@ -35,11 +35,6 @@ const RiscVGen::RiscVReg MEMBASEREG = RiscVGen::X27;
const RiscVGen::RiscVReg SCRATCH1 = RiscVGen::X10;
const RiscVGen::RiscVReg SCRATCH2 = RiscVGen::X11;
enum class MapType {
AVOID_LOAD,
ALWAYS_LOAD,
};
} // namespace RiscVJitConstants
class RiscVRegCache : public IRNativeRegCacheBase {
@ -55,8 +50,8 @@ public:
RiscVGen::RiscVReg MapGPR(IRReg reg, MIPSMap mapFlags = MIPSMap::INIT);
RiscVGen::RiscVReg MapGPRAsPointer(IRReg reg);
void MapGPRDirtyIn(IRReg rd, IRReg rs, RiscVJitConstants::MapType type = RiscVJitConstants::MapType::AVOID_LOAD);
void MapGPRDirtyDirtyInIn(IRReg rd1, IRReg rd2, IRReg rs, IRReg rt, RiscVJitConstants::MapType type = RiscVJitConstants::MapType::AVOID_LOAD);
void MapGPRDirtyIn(IRReg rd, IRReg rs, bool avoidLoad = true);
void MapGPRDirtyDirtyInIn(IRReg rd1, IRReg rd2, IRReg rs, IRReg rt, bool avoidLoad = true);
// Returns a RISC-V register containing the requested MIPS register.
RiscVGen::RiscVReg MapFPR(IRReg reg, MIPSMap mapFlags = MIPSMap::INIT);