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Merge pull request #17732 from unknownbrackets/ir-minor

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riscv: Avoid unaligned mem combine in IR
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Henrik Rydgård 2023-07-17 01:42:30 +02:00 • committed by GitHub
commit 9bef58b7f5
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2 changed files with 6 additions and 2 deletions
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3
Core/MIPS/IR/IRInterpreter.cpp
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@ -1053,7 +1053,6 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) {
inst++;
}
// If we got here, the block was badly constructed.
Crash();
// We hit count. If this is a full block, it was badly constructed.
return 0;
}

5
Core/MIPS/IR/IRJit.cpp
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@ -15,6 +15,7 @@
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "ppsspp_config.h"
#include <set>
#include "ext/xxhash.h"
@ -49,7 +50,10 @@ IRJit::IRJit(MIPSState *mipsState) : frontend_(mipsState->HasDefaultPrefix()), m
IROptions opts{};
opts.disableFlags = g_Config.uJitDisableFlags;
// Assume that RISC-V always has very slow unaligned memory accesses.
#if !PPSSPP_ARCH(RISCV64)
opts.unalignedLoadStore = (opts.disableFlags & (uint32_t)JitDisable::LSU_UNALIGNED) == 0;
#endif
frontend_.SetOptions(opts);
}
@ -229,6 +233,7 @@ void IRJit::RunLoopUntil(u64 globalticks) {
IRBlock *block = blocks_.GetBlock(data);
u32 startPC = mips_->pc;
mips_->pc = IRInterpret(mips_, block->GetInstructions(), block->GetNumInstructions());
// Note: this will "jump to zero" on a badly constructed block missing exits.
if (!Memory::IsValidAddress(mips_->pc) || (mips_->pc & 3) != 0) {
Core_ExecException(mips_->pc, startPC, ExecExceptionType::JUMP);
break;