From d4e689b09665acb10b81f9ca3830bb8606630aff Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sun, 16 Jul 2023 16:19:53 -0700 Subject: [PATCH 1/2] irjit: Allow IRInterpret() on partial block. For later if we want to fallback from native to IR interpret. --- Core/MIPS/IR/IRInterpreter.cpp | 3 +-- Core/MIPS/IR/IRJit.cpp | 1 + 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Core/MIPS/IR/IRInterpreter.cpp b/Core/MIPS/IR/IRInterpreter.cpp index 52ea205375..5b858bc1b3 100644 --- a/Core/MIPS/IR/IRInterpreter.cpp +++ b/Core/MIPS/IR/IRInterpreter.cpp @@ -1053,7 +1053,6 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) { inst++; } - // If we got here, the block was badly constructed. - Crash(); + // We hit count. If this is a full block, it was badly constructed. return 0; } diff --git a/Core/MIPS/IR/IRJit.cpp b/Core/MIPS/IR/IRJit.cpp index 37860f1564..5b882c2d5f 100644 --- a/Core/MIPS/IR/IRJit.cpp +++ b/Core/MIPS/IR/IRJit.cpp @@ -229,6 +229,7 @@ void IRJit::RunLoopUntil(u64 globalticks) { IRBlock *block = blocks_.GetBlock(data); u32 startPC = mips_->pc; mips_->pc = IRInterpret(mips_, block->GetInstructions(), block->GetNumInstructions()); + // Note: this will "jump to zero" on a badly constructed block missing exits. if (!Memory::IsValidAddress(mips_->pc) || (mips_->pc & 3) != 0) { Core_ExecException(mips_->pc, startPC, ExecExceptionType::JUMP); break; From e4f9c72fe9b01cc984dbfa7538ebad5babad2ddb Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sun, 16 Jul 2023 16:20:58 -0700 Subject: [PATCH 2/2] riscv: Avoid unaligned mem combine in IR. --- Core/MIPS/IR/IRJit.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Core/MIPS/IR/IRJit.cpp b/Core/MIPS/IR/IRJit.cpp index 5b882c2d5f..6a82ec1f7c 100644 --- a/Core/MIPS/IR/IRJit.cpp +++ b/Core/MIPS/IR/IRJit.cpp @@ -15,6 +15,7 @@ // Official git repository and contact information can be found at // https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. +#include "ppsspp_config.h" #include #include "ext/xxhash.h" @@ -49,7 +50,10 @@ IRJit::IRJit(MIPSState *mipsState) : frontend_(mipsState->HasDefaultPrefix()), m IROptions opts{}; opts.disableFlags = g_Config.uJitDisableFlags; + // Assume that RISC-V always has very slow unaligned memory accesses. +#if !PPSSPP_ARCH(RISCV64) opts.unalignedLoadStore = (opts.disableFlags & (uint32_t)JitDisable::LSU_UNALIGNED) == 0; +#endif frontend_.SetOptions(opts); }