Marco Satti
|
0155f0df33
|
Change the vmMain variable in each subclass to non-const, allowing emulation to be stopped.
|
2016-09-24 13:31:33 +08:00 |
|
Marco Satti
|
5ef9224fa6
|
Change EE core exception model (again) from a queue to a single state... A queue is unnecessary, I believe.
|
2016-09-23 20:38:53 +08:00 |
|
Marco Satti
|
a044e086b1
|
Major change to the emulator loop - added in a way to synchronise everything properly. Starting to run into performace issues with the bitfield storage object... Need to look into it, not sure why.
|
2016-09-23 16:22:54 +08:00 |
|
Marco Satti
|
ad97523489
|
Moved COP1.ACC initialisation from header to unit file... not sure why this compiled before..?
|
2016-09-20 17:21:39 +08:00 |
|
Marco Satti
|
2629c6dd45
|
Rename COP0 and COP1 bitfield registers to have COPx infront. Currently reading through the DMAC documentation.
|
2016-09-20 17:14:39 +08:00 |
|
Marco Satti
|
21bdb7171e
|
Added in the EE timers functionality. One thing I have figured out that wasnt clear before - a 'clock' from a crystal is regarded as an 'event' in programming, and a 'signal' is an 'environment variable'.
|
2016-09-19 17:03:36 +08:00 |
|
Marco Satti
|
40b6fa48f9
|
I think I finally figured out how the timers should work.. Based of the old PCSX2 method of using the ee core instruction cycles for busclk. Still unsure of how h-blnk will work, and gate logic. Also added preperation for specific EE registers.
|
2016-09-15 22:31:10 +08:00 |
|
Marco Satti
|
c69de6564c
|
Rename the current TimerHandler to EECoreTimerHandler so to not confuse between the EECore.COP0.Count/Compare and the 4 x EE Timer's
|
2016-09-14 18:19:49 +08:00 |
|
Marco Satti
|
b870cb136a
|
Forgot to check the COP0.Status IM2 bit before sending the exception to be processed. Also, having a hard time figuring out how to implement the external timers..
|
2016-09-11 21:31:44 +08:00 |
|
Marco Satti
|
5f7b1cf64c
|
Framework for the EE (DMAC, INTC, etc) put into place.
|
2016-09-11 02:17:49 +08:00 |
|
Marco Satti
|
88e004937b
|
Change the Int exception info type flag names to reflect the signal's, not the EE Core register names.
|
2016-09-10 22:18:10 +08:00 |
|
Marco Satti
|
2405b67ba0
|
Implemented properly all of the EE registers, VU memories and GS privileged registers as defined on page 21 - 26. Moved a few definitions around to better reflect the structure and scope of them.
|
2016-09-10 14:34:13 +08:00 |
|
Marco Satti
|
fd543e0e83
|
Begin work on implementing the EE registers, and some cleanup effort (especially with regards to how logging works).
|
2016-09-05 19:15:39 +08:00 |
|
Marco Satti
|
3c28e1dca1
|
Change the bitfield register map key from std::string to const char *, as its becoming more of a performance bottleneck.
|
2016-09-05 00:00:26 +08:00 |
|
Marco Satti
|
4241ce7330
|
Cleaned up the SIO_TXFIFO message functionality to use std::string.
|
2016-09-04 22:36:31 +08:00 |
|
Marco Satti
|
a468eecbc9
|
Oh god that was an embarrasing mistake.. Used logical OR instead of bitwise OR in calculating PS2 physical addresses. Spent a while tracking this down...
|
2016-09-03 20:31:25 +08:00 |
|
Marco Satti
|
751f90c5e0
|
Made a mistake in initalising objects...
|
2016-09-02 20:45:55 +08:00 |
|
Marco Satti
|
6a98fbd0e9
|
Reworked the includes - compile times were getting long so tried to use forward declarations where possible and only use headers for declarations.
|
2016-09-02 15:21:25 +08:00 |
|
Marco Satti
|
2c12d62bd5
|
Almost finished with the MCH EE register region... Too tired to continue :(.
|
2016-09-01 22:56:58 +08:00 |
|
Marco Satti
|
130893cb02
|
Start adding in proper EE registers, such as the SIO etc. Custom functionality is able to be done (thanks to the VM MMU rework in the last couple of commits), so that special registers (*undocumented*... thanks Sony) can be implemented without much spaghetti code.
|
2016-09-01 22:04:38 +08:00 |
|
Marco Satti
|
26ab25b49f
|
Fixed up the MULT/MULTU instructions (oops), BIOS now gets to reading 0x1000f440 but reads the wrong value - need to implement this EE register properly. Something to do with MCH_RICM/DRD but pcsx2 says information lacking...
|
2016-09-01 16:29:11 +08:00 |
|
Marco Satti
|
89821599bc
|
Reworked the VM MMU slightly, to operate based on read/write functions (and by extension, "storage objects"), which allows for regions of the PS2's physical memory to act in special ways - for example, the EE register 'reserved' regions, where writes are now disregarded and reads return 0.
|
2016-09-01 00:55:08 +08:00 |
|
Marco Satti
|
58659dc366
|
Implemented EE Core cycle counting and COP0.Count/COP0.Compare updating/interrupt. BIOS progresses until it tries to do something with 0x1000F430, which I can't find any description of, but its in the EE register region.
|
2016-08-30 23:31:01 +08:00 |
|
Marco Satti
|
2f8f2f193a
|
Fixed up many instruction errors - BIOS now loads correctly until it starts checking the timers - which havent been fully implemented yet! Took me almost 3 hours to fix up the ANDI instruction bug, which gives you an idea of how hard it is to find them :).
|
2016-08-30 15:24:18 +08:00 |
|
Marco Satti
|
19e390d5cb
|
Very happy! Got the scratchpad ram to work through the TLB/PS2 MMU. The documentation was a little confusing so glad to get it working. Next problem: When an exception handler resumes, it is at the wrong PC (+4 more than it should be).
|
2016-08-29 18:00:01 +08:00 |
|
Marco Satti
|
11e1885409
|
Forgot to return early when an exception is raised - added in return statements.
|
2016-08-28 14:07:47 +08:00 |
|
Marco Satti
|
14291c8bd3
|
Almost got the TLB working properly - something wrong with the first tlb entry the bios writes... Need to investigate it.
|
2016-08-28 12:32:06 +08:00 |
|
Marco Satti
|
72146199c1
|
Finished the exceptions rewrite, which can make it thread safe.
|
2016-08-27 02:12:23 +08:00 |
|
Marco Satti
|
179cd2df47
|
The exception model currently in place is not going to work in a threaded setting - need to rework it. From looking at the PCSX2 source code, they check if any exceptions have been raised after each jump-type instruction (polling system). Changes are in progress to reflect a polling method. Also added in specific exception functionality, including external exception parameters needed.
|
2016-08-25 00:17:45 +08:00 |
|
Marco Satti
|
06b899ac48
|
Preping EE register implementations (starting to work on the contents in EE Users Manual).
|
2016-08-23 17:21:25 +08:00 |
|
Marco Satti
|
9fd8ebc93b
|
Fixed up the kernel mode detection (thanks to gregory @ pcsx2), fixed up the ORI instruction. Stops execution on accessing the EE registers, which is where it should stop for now.
|
2016-08-21 23:34:31 +08:00 |
|
Marco Satti
|
8a8a018057
|
Milestone commit! Can now launch the EECore interpreter, and start emulation. There are a few remaining intstructions to implement (TLB* being the more important ones), and the interpreter also doesnt get far before a runtime_error is raised... but it is progress :).
|
2016-08-21 12:13:00 +08:00 |
|
Marco Satti
|
7aa8e266ae
|
All remaining EECore instructions completed, just need to determine how to set PC for each instruction and figure out branch delays etc.
|
2016-08-19 00:38:05 +08:00 |
|
Marco Satti
|
7dd81de250
|
Added in Special data transfer instructions, and checking for cop0 usability before operating on the registers.
|
2016-08-18 15:54:02 +08:00 |
|
Marco Satti
|
76c787f999
|
Store mem instructions done.
|
2016-08-17 23:24:35 +08:00 |
|
Marco Satti
|
f591c8c38e
|
Finished Load instructions.
|
2016-08-17 13:32:39 +08:00 |
|
Marco Satti
|
bc1c3d13e4
|
Forgot to add in my FPU notes I made a while back.
|
2016-08-15 18:34:46 +08:00 |
|
Marco Satti
|
054a216a61
|
Trialing another method of throwing exceptions - for example, within the COP1 registers, they now check that COP1 is available before commiting a read or write.
|
2016-08-15 18:02:04 +08:00 |
|
Marco Satti
|
72edb8355b
|
Re-organisation in preparation for the load to memory instructions... I hope I have it right this time. All of the EECore instruction implmentations have been changed to member functions as the memory instructions rely on the MMU, which is easily accessed through the InterpreterEECore class.
|
2016-08-15 01:45:59 +08:00 |
|
Marco Satti
|
53e055e55c
|
Done Reg transfer instructions.
|
2016-08-14 01:20:03 +08:00 |
|
Marco Satti
|
f9c9ed0da3
|
Fix VS filters.
|
2016-08-13 15:46:10 +08:00 |
|
Marco Satti
|
7d393a76ad
|
Finished Others instructions. 4 pages to go.
|
2016-08-13 15:02:24 +08:00 |
|
Marco Satti
|
ec3f5e0a36
|
Implemented Reordering instructions. Renamed EECoreFPUUtil to EECoreCOP1Util so there is no confusion (I said before that I would try to use COPx consistently instead of eg FPU).
|
2016-08-13 13:46:37 +08:00 |
|
Marco Satti
|
733afd34be
|
DFC and min/max and compare done... 5 pages to go :).
|
2016-08-13 00:24:16 +08:00 |
|
Marco Satti
|
737e420ef6
|
Finished logical implementations.
|
2016-08-12 22:42:45 +08:00 |
|
Marco Satti
|
d735059e0f
|
Started Logical instructions.
|
2016-08-12 19:59:01 +08:00 |
|
Marco Satti
|
68f430e824
|
Shift instructions done.
|
2016-08-12 19:49:22 +08:00 |
|
Marco Satti
|
cdbbc406c0
|
Fix VS filter hierarchy.
|
2016-08-12 14:20:18 +08:00 |
|
Marco Satti
|
70bbb472f4
|
Finished float arithmetic instructions. Next is shift instructions.
|
2016-08-12 13:25:26 +08:00 |
|
Marco Satti
|
aeef21a1f5
|
Unfortunately the FPR functionality talked about in last commit cant happen - unless the instruction context is parsed to the write, there is no way to determine which flags to set... so it basically becomes useless. It still helps for ZeroRegister128_t and PCRegister32_t, so I will keep it for now. Began work on EECoreFPUUtil is a new static class for helping with the FPU instructions.
|
2016-08-12 11:37:56 +08:00 |
|