Marco Satti
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76091d9252
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Changed around some debug stuff - last commit (SBUS fixes) actually fixed the OSDSYS load problem: "[Debug] EE SIO Message: # Loader 'rom0:OSDSYS':pc=00200008", which I didn't notice! I'm still spending a bit of time to double check the DMA logic.
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2017-03-12 21:16:44 +08:00 |
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Marco Satti
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e138a0ac59
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Moved some of the SBUS register update logic to the IOP side, so it now obeys the start / finish order. Updated the DMAC logic of EE and IOP to check for appropriate read/write FIFO sizes (used for debugging).
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2017-03-11 00:42:09 +08:00 |
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Marco Satti
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770f3f6909
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Fix up the DMAC accuracy option for quicker debugging. Currently investigating the "failed to load OSDSYS".
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2017-03-10 14:56:05 +08:00 |
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Marco Satti
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0f92f3e2f9
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Fixed up the load memory instructions - now gets to: "[Debug] EE SIO Message: # Loader: can't load rom0:OSDSYS" :)
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2017-03-10 00:59:12 +08:00 |
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Marco Satti
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6e7031d570
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Update the readme a bit... been a while.
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2017-03-08 14:50:13 +08:00 |
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Marco Satti
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21121a30a3
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Update to VS2017.
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2017-03-08 13:23:19 +08:00 |
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Marco Satti
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c25c79290c
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Added in a system skip cycles option to consume all ticks for a run - for systems such as the DMAC's, where nothing will change if no DMA transfer is in process (wasting energy on nothing). Multi threaded mode needs to be tested with it. Reworked the IOP timers overflow check - not sure why, but there was a huge perf increase (no obvious changes, probably a lot of cache misses).
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2017-03-07 23:35:04 +08:00 |
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Marco Satti
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5fc137163a
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Fixed up the interrupt/exception PC stuff for the ??? time... Still not happy with it but it works. IOP and EE now sitting in idle loops (interrupts enabled), which is good. Onto the VPU's!
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2017-03-07 13:33:44 +08:00 |
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Marco Satti
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0d5159440b
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Fixed up the EE DMAC interrupt not getting handled properly. Need to investigate the IOP infinite loop next (no interrupts enabled).
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2017-03-05 20:21:17 +08:00 |
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Marco Satti
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436dec2b0d
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Implemented the IOP source chain mode DMA transfer! EE and IOP are now communicating with each other!
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2017-03-05 15:22:18 +08:00 |
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Marco Satti
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717632d7d7
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Got IOP DMAC channel SIF1 to recieve data properly in (dest) chain mode - now working on implementing source chain mode to work (for SIF0).
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2017-03-04 23:14:31 +08:00 |
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Marco Satti
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506a741a0d
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Cleanup of the IOP and EE DMAC's based upon new info from wisi and SP193, getting ready for IOP's chain mode.
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2017-03-03 13:51:34 +08:00 |
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Marco Satti
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3e2c08eed4
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Git sync commit.
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2017-02-23 17:06:34 +08:00 |
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Marco Satti
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999d7402e3
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Fix dword ordering of the u128 type, which fixes the FIFO queue word ordering. Currently investigating the IOP SIF1 chain mode (not documented except for PCSX2).
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2017-02-22 22:51:57 +08:00 |
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Marco Satti
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513bb452bd
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Change the COP0 operating context functions to be 1 function.
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2017-02-21 16:39:24 +08:00 |
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Marco Satti
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91bcd88dd1
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Merge branch 'gs-pcrtc-test'
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2017-02-20 18:53:11 +08:00 |
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Marco Satti
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92884aaae8
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Still not finished with the CRTC, but I wil look at it later - sorted out the pixel clock stuff, how to interrupt the EE/IOP intc, and the timer gate functionality for now.
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2017-02-20 18:47:23 +08:00 |
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Marco Satti
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0ef78b3084
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Initial test of the PCRTC - based of guesses (calculating a pixel clock, using that for hblank and vblank).
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2017-02-15 20:04:15 +08:00 |
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Marco Satti
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eaeea2066e
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Merge branch 'threading-test' - although MT mode is not quite ready (race condition issues), the ST mode was updated in the process (stable).
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2017-02-04 15:26:05 +08:00 |
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Marco Satti
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a26e84c42f
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Changed the time slice VM options (MT and ST) to a single option, as both are useless when only 1 mode can be selected.
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2017-02-04 11:58:05 +08:00 |
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Marco Satti
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fe7fe047f7
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Got logging working again, fixed up single threaded mode, added in a VM option for time slice's per VM run() instead of fixed values.
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2017-02-04 00:36:22 +08:00 |
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Marco Satti
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4e638f247b
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Major refactor & clean, implemented threading (still not sure on best practice but it seems fairly simple code wise), added system biasing / persistant clock speed state, stuffed up logging however, need to fix that.
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2017-02-03 21:32:00 +08:00 |
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Marco Satti
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2340a10aa7
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Working POC of threading. Still need to make the bus writes (in PhysicalMMU_t) atomic, but for now it works without it (DMA transfers I imagine will need this). Will also refactor the VM manager shortly.
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2017-01-30 20:33:39 +08:00 |
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Marco Satti
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cca0ab5b01
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Initial threading test try - not currently working.
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2017-01-28 16:17:20 +08:00 |
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Marco Satti
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65f1287dc5
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Refactored a lot of code, moved the EE and IOP core's MMU and Exception handlers into the base core class logic. Currently brainstorming over multi-threading, as this is a good time to put it in.
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2017-01-27 22:47:02 +08:00 |
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Marco Satti
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12cd7f1e4f
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Fixes for interrupt handling...
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2017-01-22 20:21:22 +08:00 |
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Marco Satti
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3af76911eb
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Initial commit of working IOP timers.. still a lot left unimplemented, but basics (sysclock count, interrupting) working.
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2017-01-21 17:32:05 +08:00 |
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Marco Satti
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70cba8c009
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Implemented IOP timers resources, logic to follow.
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2017-01-19 19:21:52 +08:00 |
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Marco Satti
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5e48cefa6f
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Implemented most of the SBUS registers.
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2017-01-19 17:21:11 +08:00 |
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Marco Satti
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a7cae2e5ef
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WIP on implementing SBUS register functionality. DMA and FIFO stuff done.
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2017-01-18 21:27:52 +08:00 |
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Marco Satti
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c11b989f67
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Moved more interrupt logic to registers.
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2017-01-17 00:00:56 +08:00 |
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Marco Satti
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55aee83090
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Begin implementing SBUS register functionality. Moved some parts of code from logic components into registers, such as determining if an interrupt should be raised. There is a blurry line here.. when should I put things into registers (event based) and when should I put things into logic components (polling based)? I have currently defined this line as "its ok to put things in registers that do not interface with other registers outside its 'area'", exceptions being made for fully un-reversed engineered parts such as the SBUS registers/logic.
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2017-01-16 21:04:38 +08:00 |
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Marco Satti
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ead73a2e67
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Moved setFieldValue to an inline function.
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2017-01-16 10:33:16 +08:00 |
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Marco Satti
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e96661bfba
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Cleanup.
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2017-01-15 21:58:26 +08:00 |
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Marco Satti
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90b6b7de1d
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Fixed up a few exception handling errors - in particular, the EE and IOP Core's now increment the PC before executing the instruction.
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2017-01-15 16:17:26 +08:00 |
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Marco Satti
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12792cc78a
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Changed interrupts to a full polling method - currently level interrupt triggered, but can be edge if needed. Still investigating a bug to do with the IOP.COP0.Status where it doesnt always re-enable interrupts.
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2017-01-13 22:52:27 +08:00 |
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Marco Satti
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a473c16894
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Small optimisation to both DMAC logic.
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2017-01-13 14:35:25 +08:00 |
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Marco Satti
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c1a6f7b264
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Added in separate MIPS branch delay object type, split register debugging into reads and writes.
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2017-01-13 00:17:18 +08:00 |
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Marco Satti
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a86f11028e
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Few small fixes to interrupt handling. Still not working properly, currently debugging.
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2017-01-11 19:07:53 +08:00 |
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Marco Satti
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cf9f784eda
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FeelsReallyGoodMan - EE and IOP are beginning to communicate through the SBUS (DMA transfers)! IOP now interrupting on SIF1 completing. Will need to change the way interrupt exceptions are generated as currently the IOP INTC is sending one every tick (and getting handled meaning no progression in the IOP Core). Reworked some COP0 BitfieldRegister32's that were basically equivilant to a Register32 (simplified). Added in an initalise virtual function to the registers. General reorganisation.
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2017-01-09 19:00:07 +08:00 |
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Marco Satti
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78b8b170f3
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Fixup of the exception handling for the EE and IOP cores. Now checks for masking conditions before commiting the exception (especially needed for interrupts).
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2017-01-06 12:07:58 +08:00 |
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Marco Satti
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4f8ec56862
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WIP on the IOP Dmac
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2017-01-04 14:09:55 +08:00 |
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Marco Satti
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0e4728be86
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Added in register context as a parameter when reading/writing. 2 reasons: easier debugging, and to support registers which have different functionality depending on which component accessed it (ie: EE or IOP). This will be useful, for example, with the SBUS registers.
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2017-01-03 18:13:34 +08:00 |
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Marco Satti
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706fcedd78
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Cleaned up the memory and register types - no longer have a signed/unsigned combo, instead the caller must cast the result to the appropriate type (only useful on reads in most cases). Rationale for this change is to stop duplicating custom functionality through eg: readWordU/S.
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2017-01-01 19:00:42 +08:00 |
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Marco Satti
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23e7301aa4
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Initial IOP INTC (INTR?) commit - still to decypher bitfields within the registers.
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2016-12-29 22:23:21 +08:00 |
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Marco Satti
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62654cdfe1
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Cleanup.
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2016-12-26 00:02:51 +08:00 |
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Marco Satti
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aaf895f7c2
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Add in debug syscall tables for the EE and IOP.
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2016-12-24 16:31:19 +08:00 |
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Marco Satti
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f04e6d795c
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Remove getPCValue() from PCRegister32_t - not needed, use normal register read functions.
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2016-12-23 21:54:33 +08:00 |
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Marco Satti
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5863b6b252
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WIP on IOP DMAC registers. Changed FIFO queue to use u32 as base type, since the IOP needs to read from it.
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2016-12-23 00:48:23 +08:00 |
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Marco Satti
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9e0af0acb9
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Begin adding in IOP DMAC resources/system logic.
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2016-12-22 18:43:23 +08:00 |
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