Marco Satti
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fd36c6dd63
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Small fix to the u128 type which caused incorrect values to be later read. Removed the source chain first cycle stuff - didnt realise the PS2 OS sets TADR before turning the dma channel on.
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2016-12-22 00:40:44 +08:00 |
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Marco Satti
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0fd155193b
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Moved channel related functions into the channel type instead of the DMAC system. Also got rid of the slice channel count stuff - implementation was wrong and correct way doesn't make sense in an emulator (if I read it correctly this time). Probably need to write the IOP DMAC system now, wont be able to progress any further until I do so.
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2016-12-21 14:26:59 +08:00 |
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Marco Satti
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b645357eaa
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EE DMAC now works somewhat - EE is writing data to the SIF1 channel (there is no IOP DMAC to recieve it yet). Still a bit more work to do. IOPCore stuck in infinite loop, presumably waiting for an interrupt, while EECore is watching an address, presumably for the IOP to write to it.
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2016-12-20 23:24:49 +08:00 |
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Marco Satti
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2194330ce5
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Added in abstraction for read/writing 128-bit primatives to memory, registers, etc. DMAC now crashes due to no data being available in the associated fifo queue... Need to add a way to return early and try again next cycle if this occurs.
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2016-12-18 22:31:42 +08:00 |
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Marco Satti
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0aab1549bb
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Brainstorming a bit for the EE DMAC fixes..
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2016-12-17 23:03:48 +08:00 |
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Marco Satti
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3974afb750
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Put in more SIF registers (SBUS), now crashes in the EE DMAC SIF0 channel system - missing TADR register. Will have to invesigate more with PCSX2 as the manual clearly says there isn't one, but PCSX2 supports chain (tag) mode implying there is one.
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2016-12-14 17:59:44 +08:00 |
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Marco Satti
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54cc1fd292
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IOP now has all registers implemented properly, in step with before. Changed the MappedRegister wrapper classes to allow aligned register access, where appropriate.
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2016-12-14 16:52:08 +08:00 |
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Marco Satti
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b26b1a9211
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Renamed registers to be more consistent, changed the register mapping wrappers to allow accesses other than the nominated size (returns LSB's).
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2016-12-13 23:18:15 +08:00 |
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Marco Satti
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71b7bbbf68
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Change ZeroRegister types to ConstantRegister - allows the user to set specific constant values instead of just 0 (defaults to 0 if no parameter specified). WIP on adding IOP DMAC stuff.
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2016-12-13 18:33:46 +08:00 |
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Marco Satti
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613fa4aa1c
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Starting to properly implement the IOP now. Will probably take a while to go through PCSX2's source code.
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2016-12-13 00:48:07 +08:00 |
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Marco Satti
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6a65d07cfc
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Small speedups for debugging (inlining). Small cleanup/reorganisation of the component timing.
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2016-12-10 00:19:44 +08:00 |
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Marco Satti
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cf39c4a94b
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Started adding in a bunch of IOP registers/memory (CDVD & ROM1, EROM, ROM2).
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2016-12-06 17:57:42 +08:00 |
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Marco Satti
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dd40cc16fb
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Small bug fixes in the EECore FPU and MMU.
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2016-11-30 00:20:52 +08:00 |
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Marco Satti
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8ef9059f98
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Bug fix for the wrong PA's being returned for VA's in the EE Core - spent a whole day tracking this one down! When debugging, it was acutally overwriting the instructions already there causing a large amount of confusion on my part...
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2016-11-29 20:29:41 +08:00 |
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Marco Satti
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777d267389
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Begin implementing the VU instructions. Changes to the way FPU values are calculated - when calling the format function it will fill in a list of flags needed by the EE Core FPU and VU units.
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2016-11-28 21:02:55 +08:00 |
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Marco Satti
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7ef5cd173a
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Added in the VU0/1 registers (and other. misc ones)
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2016-11-26 16:38:39 +08:00 |
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Marco Satti
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04a3174ff2
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Cleanup, get rid of mostly useless get functions, move instruction exception raising code to helper functions.
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2016-11-19 03:03:39 +08:00 |
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Marco Satti
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96fbe08138
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VU structure work. EE Core now delegates COP2 instructions to the VU0 unit.
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2016-11-18 20:29:05 +08:00 |
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Marco Satti
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41010d6ebc
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COP2 instruction table and definitions added, still need to implement the actual code. Added additional field extraction functions to a new EECoreInstruction_t that is based on the MIPS one.
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2016-11-17 18:01:15 +08:00 |
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Marco Satti
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124f31794f
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WIP on the VIF, VU and COP2 (VU0 connection) of the EE Core.
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2016-11-16 20:13:04 +08:00 |
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Marco Satti
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13c970b8eb
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Begin work on the VIF system. Added in the VU zero register.
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2016-11-12 20:09:46 +08:00 |
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Marco Satti
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51086c5657
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Implemented more MappedRegister_t types, set up the VU0/1 physical memory map framework.
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2016-11-11 16:18:44 +08:00 |
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Marco Satti
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f743c0a8d7
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A lot of organisation again. I had to remove the direct mapping ability of MappedMemory_t (now just Memory_t) as VU0 requires its memory be mapped in two places - it was getting messy with image mappings everywhere. There is now a wrapper class to map Memory_t. There are new mapMemory() functions to create the wrappers automatically.
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2016-11-10 15:28:10 +08:00 |
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Marco Satti
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056f2634d4
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Removed an unused include.
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2016-10-30 21:28:33 +08:00 |
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Marco Satti
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7d69528016
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Structual changes needed for writing the upcoming VU code. Removed the class / idea of 'bitfield memory 32' and instead changed things to use BitfieldRegister32_t. In order to map a register (into PhysicalMMU_t), a new compatibility layer MappedRegister32_t has been created instead. Any MappedMemory_t class and child classes remain intact, they can still be mapped directly.
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2016-10-30 21:26:00 +08:00 |
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Marco Satti
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7796445880
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Cleanup.
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2016-10-28 23:36:19 +08:00 |
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Marco Satti
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1e8688fd60
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Added in a few more memory mappings, fixed the EE Core and IOP MMU's to recognise when a read or write is occuring (helps with throwing exceptions and checking for the isolate cache condition).
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2016-10-28 15:16:21 +08:00 |
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Marco Satti
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73d33b244b
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Fixed up the IOP's COP0 registers, added a check for the IsC bit when writing to IOP's main memory. Discards the write if set.
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2016-10-25 23:54:29 +08:00 |
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Marco Satti
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a321ce4bf5
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Tracked down a bug preventing IOP progress due to it writing to the BIOS area (???) - made ROMappedMemory_t which discards writes and the BIOS is now subclassed of that instead.
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2016-10-23 22:33:50 +08:00 |
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Marco Satti
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415861a532
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Move the IOP core into its proper hierarchy (IOPCore).
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2016-10-22 17:35:37 +08:00 |
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Marco Satti
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9e0d685a74
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Put in some of the IOP undocumented memory accesses.. the PC now enters the main memory for execution!
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2016-10-21 22:21:21 +08:00 |
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Marco Satti
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85470b6e27
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Moved the VM MMU to a separate type under PS2Resources - the IOP has its own address space apparently so we can reuse it.
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2016-10-21 20:41:36 +08:00 |
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Marco Satti
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f0ad6f2145
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Started working on the IOP - got the main loop going with basic MIPS instructions done. Added in a method for sending clock events to components and updating the individual timings for each clock source. Currently, components such as the DMAC, INTC will be renamed to EECoreDMAC etc once the IOP components are put in.
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2016-10-18 09:58:37 +08:00 |
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Marco Satti
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3e01b4b1fb
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Implemented DMAC stall control.
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2016-10-12 12:57:27 +08:00 |
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Marco Satti
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a94391b829
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Finished interleaved DMAC mode, organised EE register resources structure into sub systems.
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2016-10-09 18:47:15 +08:00 |
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Marco Satti
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91c8bcdc78
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Small cleanup to the DMAC code. Taking a break for a bit perhaps, will start on IOP or VIF/VU when I resume (after the rest of the DMAC).
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2016-10-06 22:57:58 +08:00 |
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Marco Satti
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cf22906291
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DMA tag instructions done.
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2016-10-05 13:02:11 +08:00 |
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Marco Satti
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d665c8d206
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Chain mode mostly done, just need to implement tag ID actions.
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2016-10-04 23:36:03 +08:00 |
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Marco Satti
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49febe88d7
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More on DMAC.
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2016-10-04 00:18:09 +08:00 |
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Marco Satti
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0b21031341
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Organisation, more work on DMAC source chain mode (currently reading though PCSX2 source code)
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2016-10-03 17:10:36 +08:00 |
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Marco Satti
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c87ecbe9b4
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Try this for calculating physical mem addresses - can't test for now though.
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2016-09-30 21:06:31 +08:00 |
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Marco Satti
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30f1f2792c
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Reorganised the EE Core MMU.. I think there is something wrong with stage 4 lookup, currently debugging it.
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2016-09-30 17:57:20 +08:00 |
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Marco Satti
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10c9c188ca
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Fix up the mask generator function for when length = 32. x86 only allows shifting for 0-31, so need a special condition for 32.
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2016-09-30 09:10:56 +08:00 |
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Marco Satti
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bc18d72e5e
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Removed boost dependencies, and updated documentation.
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2016-09-29 22:54:25 +08:00 |
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Marco Satti
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f8a1b96099
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Ok - moved to a C array for the bitfield map. Should not be an issue any more... It works (good), and the only sanity checking done is on the index supplied.
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2016-09-29 22:24:22 +08:00 |
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Marco Satti
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1b056fce38
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Renamed StorageObject -> MappedMemory. Moved bitfield map into its own type class which is extended by the registers and mapped memory... Something seems to have broken performance though...
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2016-09-28 23:20:02 +08:00 |
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Marco Satti
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1ba1c69dea
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Done a bit more on the DMAC. Normal mode almost done.
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2016-09-28 13:34:42 +08:00 |
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Marco Satti
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8b38815735
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Added in bitfield DMAC channel registers.
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2016-09-25 19:48:32 +08:00 |
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Marco Satti
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4d78f68122
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As you have to generate symlinks to the boost headers, mark in the gitmodules file that we can safely ignore modifications in the boost submodule folder.
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2016-09-24 17:02:34 +08:00 |
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Marco Satti
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7d93972e73
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Switched from std::unordered_map to boost::container::flat_map... much better when run under the optimised build. From 20s run time to almost nothing!
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2016-09-24 16:56:24 +08:00 |
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