1647 commits

Author	SHA1	Message	Date
Dillon Beliveau	34d00d15f6	Merge branch 'master' into dynarec_v2	2023-04-29 11:16:33 -07:00
Dillon Beliveau	41708b9350	recording demos	2023-04-29 11:16:16 -07:00
Dillon Beliveau	6b7ed7941c	Get register type properly	2023-04-23 19:22:31 -07:00
Dillon Beliveau	f76ad08062	CP0 regs + TLB instructions, enough to get GoldenEye working	2023-04-23 16:28:53 -07:00
Dillon Beliveau	f37d9fc568	Sort block list so matching sysconfig is at the head when a miss occurs	2023-04-18 22:41:57 -07:00
Dillon Beliveau	1b3e930857	spilled support for xor imm	2023-04-16 15:49:20 -07:00
Dillon Beliveau	a79631314e	remove breakpoint	2023-04-16 15:05:52 -07:00
Dillon Beliveau	2465812502	fix a bug in DIV	2023-04-16 14:44:54 -07:00
Dillon Beliveau	b9801847ed	dynarec compare fixes + support for tas movies	2023-04-16 14:44:46 -07:00
Dillon Beliveau	ce598123d0	cop1 unusable exceptions are implemented in the jit now	2023-04-15 12:23:07 -07:00
Dillon Beliveau	8c81117c73	more float conversions	2023-04-15 12:17:49 -07:00
Dillon Beliveau	01b41aaeda	detect and handle branch in branch delay slot	2023-04-09 15:43:43 -07:00
Dillon Beliveau	73f234b76a	implement more MFC0 and DMFC0 registers	2023-04-09 15:24:53 -07:00
Dillon Beliveau	bc2c546668	compare u32 immediate fixes	2023-04-09 15:24:30 -07:00
Dillon Beliveau	a43437f63e	division improvements	2023-04-09 15:24:19 -07:00
Dillon Beliveau	bba290b97e	spilled reg handling in shifts	2023-04-09 15:22:30 -07:00
Dillon Beliveau	801c697bf6	dsrav	2023-04-09 15:11:39 -07:00
Dillon Beliveau	125e799ef9	set prev_branch = branch before handling TLB miss pc exception	2023-04-09 12:49:40 -07:00
Dillon Beliveau	ff51ff3ad7	pass bus access correctly during constant propagation (even though it shouldn't matter)	2023-04-09 12:36:48 -07:00
Dillon Beliveau	f5898fff12	check mult hi and mult lo in dynarec compare	2023-04-09 12:22:22 -07:00
Dillon Beliveau	ef5b74aca6	FPU register behavior improvements	2023-04-09 12:22:04 -07:00
Dillon Beliveau	52530fb466	lld	2023-04-09 10:29:43 -07:00
Dillon Beliveau	cf35a1d482	spilled reg handling in not_reg and add_reg_imm	2023-04-09 10:18:09 -07:00
Dillon Beliveau	40a95f83b5	ll, sc, improve conditional block exit instruction,	2023-04-08 17:31:28 -07:00
Dillon Beliveau	1a1ef04953	s64 multiply	2023-04-08 13:23:59 -07:00
Dillon Beliveau	59b37f750e	unordered float compares, dsrlv, teq	2023-04-08 10:48:14 -07:00
Dillon Beliveau	6309dfa002	set epc, xcontext, and implement dmfc0	2023-03-27 18:04:50 -07:00
Dillon Beliveau	0d1e7cf3e7	interpreter fallback when a delay slot is on a different page from its branch	2023-03-27 18:04:08 -07:00
Dillon Beliveau	7a728522cc	dmtc0 context/entryhi	2023-03-19 20:37:48 -07:00
Dillon Beliveau	25b2328ee9	check cp1 enabled	2023-03-19 15:56:46 -07:00
Dillon Beliveau	2ab8417dbc	fix rom bounds checking	2023-03-19 14:40:03 -07:00
Dillon Beliveau	dcc923ec61	"sysconfig" concept for jit blocks	2023-03-19 14:39:55 -07:00
Dillon Beliveau	d6ecee8d87	more constant propagation for FPU ops	2023-03-19 13:05:51 -07:00
Dillon Beliveau	5a25741e6d	improve mtc1/mfc1/dmtc1/dmfc1	2023-03-19 12:57:18 -07:00
Dillon Beliveau	42664ae697	xor spilled regs	2023-03-19 12:56:32 -07:00
Dillon Beliveau	b7cbccff3c	handle spilled regs in mov_reg_imm and mult_reg_imm	2023-03-19 02:14:17 -07:00
Dillon Beliveau	f1e434b345	make check_reg a macro, so that logfatals will link to the correct line	2023-03-19 01:55:48 -07:00
Dillon Beliveau	b17ef7eb29	fix tests	2023-03-19 01:43:11 -07:00
Dillon Beliveau	bf9c0a38a1	stub float round	2023-03-19 01:37:56 -07:00
Dillon Beliveau	2013b231df	dsrl32, dmfc1, dmtc1, implement float_abs_reg_reg	2023-03-19 01:29:50 -07:00
Dillon Beliveau	89847bb47c	sdl, sdr, sync, ll, sc	2023-03-19 01:06:20 -07:00
Dillon Beliveau	b920127cfd	clear FCR31 flag and cause in interpreter, when comparing	2023-03-18 17:30:33 -07:00
Dillon Beliveau	6932c7f383	check FCR31 in dynarec_compare	2023-03-18 17:30:14 -07:00
Dillon Beliveau	d8ba707f4a	Merge branch 'master' into dynarec_v2	2023-03-18 17:19:14 -07:00
Dillon Beliveau	a9071ba5b3	dynarec_compare: cleanup IPC resources at exit	2023-03-18 16:56:02 -07:00
Dillon Beliveau	bbd87af7d4	Fix FPU on Windows	2023-03-18 15:52:01 -07:00
Dillon Beliveau	1e3646457f	mov.s is an alias for mov.d	2023-03-18 15:13:34 -07:00
Dillon Beliveau	2ffc72e187	sign extend when moving a 32 bit fpu reg to a gpr	2023-03-18 15:11:49 -07:00
Dillon Beliveau	28f15455b4	incomplete s64 divides	2023-03-18 14:51:12 -07:00
Dillon Beliveau	ce699fe528	Explicit error when scheduler event nodes are exhausted	2023-03-18 14:24:22 -07:00