1647 commits

Author	SHA1	Message	Date
Dillon Beliveau	0a7311fd0f	don't shrink constants down to u32 if the sign bit is set	2023-07-22 22:05:49 -07:00
Dillon Beliveau	5bc12895b3	fix format string	2023-07-22 22:05:37 -07:00
Dillon Beliveau	dae333377b	Merge branch 'master' into dynarec_v2	2023-07-22 18:22:55 -07:00
Dillon Beliveau	38dafa90a5	Fix LL	2023-07-22 17:04:55 -07:00
Dillon Beliveau	fe8b0a59b6	support for logging CPU state	2023-07-22 17:04:47 -07:00
Dillon Beliveau	75959e5f1b	print constant type	2023-07-22 17:04:08 -07:00
Dillon Beliveau	0ce1792f34	fix JIT TLB exceptions	2023-07-22 17:03:43 -07:00
Dillon Beliveau	985c615249	fix count reg in matchjit interpreter	2023-07-22 15:06:19 -07:00
Dillon Beliveau	00c74a7329	Awful hack to fix CP0 register names in disassembly	2023-07-22 14:50:05 -07:00
Dillon Beliveau	a0bbefa4d9	software mode in compare tool	2023-07-22 14:02:02 -07:00
Dillon Beliveau	56bb6d0dac	check window initialization	2023-07-16 23:38:35 -07:00
Dillon Beliveau	cf86d0d531	fix more format specifiers	2023-07-16 22:55:22 -07:00
Dillon Beliveau	131ae1f2c5	replace more printf format specifiers with macro	2023-07-16 18:54:47 -07:00
Dillon Beliveau	09263a71c7	Merge branch 'master' into dynarec_v2	2023-07-16 18:52:51 -07:00
Dillon Beliveau	744d8ed655	use macros for format strings	2023-07-16 18:45:48 -07:00
Dillon Beliveau	7d556f46a9	add extra warning	2023-07-16 15:48:50 -07:00
Dillon Beliveau	bc2cdc1707	fix an invalid block length bug	2023-07-16 15:48:45 -07:00
Dillon Beliveau	f9a3fd6021	RDHWR	2023-07-16 14:33:09 -07:00
Dillon Beliveau	8707054bd9	tlb exceptions improvements	2023-07-16 14:29:22 -07:00
Dillon Beliveau	b74f1f11b9	tlb exceptions, wip	2023-07-15 15:33:24 -07:00
Dillon Beliveau	5a1876d46a	logtester verify cp0 cause and mi intr	2023-07-15 12:49:55 -07:00
Dillon Beliveau	22ce68e83d	interrupt timing issues	2023-07-15 12:49:45 -07:00
Dillon Beliveau	dc620ea9ef	update interrupts for ip0 and ip1	2023-07-15 11:56:59 -07:00
Dillon Beliveau	be131d52b1	logtester updates	2023-07-15 11:56:57 -07:00
Dillon Beliveau	c3e2cfd83b	Merge branch 'master' into dynarec_v2	2023-07-15 09:29:35 -07:00
Dillon Beliveau	34f70b42ac	Merge branch 'dynarec_v2' of github.com:Dillonb/n64 into dynarec_v2	2023-07-15 09:29:05 -07:00
Dillon Beliveau	e015f9dddf	don't latch pi for linux debug output	2023-07-10 13:37:36 -04:00
Dillon Beliveau	7c3af909ee	Merge branch 'dynarec_v2' into microsoft-abi	2023-07-09 00:20:47 -04:00
Dillon Beliveau	a925ba7e76	fix dangling pointer for compiler v1 and rsp	2023-07-09 00:20:24 -04:00
Dillon Beliveau	c122f9df3e	Windows support for dynarec v2 using the MS ABI	2023-07-08 18:03:29 -04:00
Dillon Beliveau	2f095b35d5	support spilling FGRs	2023-06-10 17:57:52 -07:00
Dillon Beliveau	2fed73d3c7	fix some memory errors	2023-06-10 15:10:51 -07:00
Dillon Beliveau	fc668db02e	fix unsigned divides	2023-06-10 15:10:38 -07:00
Dillon Beliveau	d6b6927275	rewrite register flushing to be more flexible when more instructions eventually throw exceptions	2023-06-10 15:10:30 -07:00
Dillon Beliveau	ba6b9a750d	allow expiring old spill spaces	2023-06-10 14:02:09 -07:00
Dillon Beliveau	3a51ada83f	mtc0 CONFIG, DMTC0 ENTRY_LO0 & ENTRY_LO1	2023-06-05 22:12:39 -07:00
Dillon Beliveau	899209351a	scd, teq, tge, tgeu, tlt, tltu, tne	2023-05-29 17:28:24 -07:00
Dillon Beliveau	6e0caa7af1	read PRId	2023-05-29 17:09:17 -07:00
Dillon Beliveau	4c6eae6915	u64 and s64 multiply	2023-05-29 17:07:54 -07:00
Dillon Beliveau	878325ff70	correctly flush fpu registers	2023-05-27 20:01:11 -07:00
Dillon Beliveau	35ccca624f	allow MTC0 watchlo in the jit	2023-05-27 16:01:59 -07:00
Dillon Beliveau	e55c144fad	various jit fixes	2023-05-27 15:56:12 -07:00
Dillon Beliveau	6d66573bad	Merge branch 'master' into dynarec_v2	2023-05-19 17:40:02 -07:00
Dillon Beliveau	6502f7d2f1	Fix two implicit fallthrough errors	2023-05-18 23:16:20 -07:00
offtkp	725c10e1fb	Eliminate evil implicit fallthrough	2023-05-19 00:45:12 +03:00
Dillon Beliveau	553e3d3eda	better constant propagation for multiplies and divides	2023-05-13 15:56:12 -07:00
Dillon Beliveau	02caf5560d	interrupts on the scheduler	2023-05-13 14:29:14 -07:00
offtkp	db288ef0cb	Support reading of ADDR_VI_H_START_REG ... The libdragon example test roms read from this register during initialization	2023-05-03 17:38:53 +03:00
Dillon Beliveau	a31d7489cc	Merge branch 'master' into dynarec_v2	2023-04-29 14:12:01 -07:00
Dillon Beliveau	8b9dccfdaa	VI timing on scheduler	2023-04-29 14:04:54 -07:00