1066 commits

Author	SHA1	Message	Date
Dillon Beliveau	9f1e3f0df7	Allow building without dynarec v1	2023-08-27 23:21:01 -07:00
Dillon Beliveau	72252bcff0	move v2_compiler_x64.c to a platform specific section	2023-08-27 22:19:04 -07:00
Dillon Beliveau	70a48ef315	move platform specific JIT code to platform specific file	2023-08-27 22:08:22 -07:00
Dillon Beliveau	06dd84da3f	implement c_nge and c_ngt in jit	2023-08-27 14:47:24 -07:00
Dillon Beliveau	a3e4b3c77e	remove some FGR size checks	2023-08-27 13:20:11 -07:00
Dillon Beliveau	a271682719	rename N64_USE_SIMD directive to N64_HAVE_SSE	2023-08-27 13:10:55 -07:00
Dillon Beliveau	182b7e2b92	Fix build on Linux	2023-08-26 23:17:18 -07:00
Dillon Beliveau	f08c2ee007	Cache TLB resolutions	2023-08-26 18:17:29 -07:00
Dillon Beliveau	390beaf4d7	swap a function pointer for virtual address resolution when changing modes	2023-08-26 13:47:21 -07:00
Dillon Beliveau	53ceffaaa3	fix unused variable warning when N64_LOG_COMPILATIONS is not defined	2023-08-25 23:44:15 -07:00
Dillon Beliveau	e30194a2bc	detect idle loops with J self; nop	2023-08-25 22:06:56 -07:00
Dillon Beliveau	d16a934c58	enable idle loop detection by default	2023-08-25 20:30:18 -07:00
Dillon Beliveau	5c6a7b6a25	basic idle loop detection	2023-08-25 20:23:38 -07:00
Dillon Beliveau	28d0f790dd	code to help me find idle loops	2023-08-25 19:57:45 -07:00
Dillon Beliveau	d32d9c49ad	minor fix, expand on comment	2023-08-25 19:56:07 -07:00
Dillon Beliveau	4a229161ac	make this a warning	2023-08-23 23:58:58 -07:00
Dillon Beliveau	0b9ff6bb0c	register spilling rework	2023-08-23 23:21:57 -07:00
Dillon Beliveau	360c2e64be	prep for register spilling rework	2023-08-23 22:34:30 -07:00
Dillon Beliveau	02e3c5be0c	don't recalculate sysconfig every time	2023-08-23 20:52:22 -07:00
Dillon Beliveau	dd5e5d4bea	split rsp link stage	2023-08-22 01:26:59 -07:00
Dillon Beliveau	6247ab3ee6	Merge branch 'master' into dynarec_v2	2023-08-22 01:26:06 -07:00
Dillon Beliveau	cccc33fd1b	fix build when building without SIMD	2023-08-05 12:25:23 -07:00
Dillon Beliveau	ec46e808b6	consistent naming	2023-08-01 22:40:13 -07:00
Dillon Beliveau	cc12fd927a	remove unused	2023-08-01 22:40:04 -07:00
Dillon Beliveau	3abd96f15a	remove unused values	2023-07-29 14:23:35 -07:00
Dillon Beliveau	6e8652d79c	reorder operations in sc and scd to match the interpreter	2023-07-23 17:35:09 -07:00
Dillon Beliveau	0f48b25fea	make the block's virtual address a compile time constant	2023-07-23 16:36:30 -07:00
Dillon Beliveau	c061b67c32	fix tlb exceptions when tlb_lookup destination reg is spilled	2023-07-22 22:06:30 -07:00
Dillon Beliveau	0a7311fd0f	don't shrink constants down to u32 if the sign bit is set	2023-07-22 22:05:49 -07:00
Dillon Beliveau	5bc12895b3	fix format string	2023-07-22 22:05:37 -07:00
Dillon Beliveau	dae333377b	Merge branch 'master' into dynarec_v2	2023-07-22 18:22:55 -07:00
Dillon Beliveau	38dafa90a5	Fix LL	2023-07-22 17:04:55 -07:00
Dillon Beliveau	75959e5f1b	print constant type	2023-07-22 17:04:08 -07:00
Dillon Beliveau	0ce1792f34	fix JIT TLB exceptions	2023-07-22 17:03:43 -07:00
Dillon Beliveau	00c74a7329	Awful hack to fix CP0 register names in disassembly	2023-07-22 14:50:05 -07:00
Dillon Beliveau	cf86d0d531	fix more format specifiers	2023-07-16 22:55:22 -07:00
Dillon Beliveau	131ae1f2c5	replace more printf format specifiers with macro	2023-07-16 18:54:47 -07:00
Dillon Beliveau	09263a71c7	Merge branch 'master' into dynarec_v2	2023-07-16 18:52:51 -07:00
Dillon Beliveau	744d8ed655	use macros for format strings	2023-07-16 18:45:48 -07:00
Dillon Beliveau	bc2cdc1707	fix an invalid block length bug	2023-07-16 15:48:45 -07:00
Dillon Beliveau	f9a3fd6021	RDHWR	2023-07-16 14:33:09 -07:00
Dillon Beliveau	8707054bd9	tlb exceptions improvements	2023-07-16 14:29:22 -07:00
Dillon Beliveau	b74f1f11b9	tlb exceptions, wip	2023-07-15 15:33:24 -07:00
Dillon Beliveau	22ce68e83d	interrupt timing issues	2023-07-15 12:49:45 -07:00
Dillon Beliveau	dc620ea9ef	update interrupts for ip0 and ip1	2023-07-15 11:56:59 -07:00
Dillon Beliveau	34f70b42ac	Merge branch 'dynarec_v2' of github.com:Dillonb/n64 into dynarec_v2	2023-07-15 09:29:05 -07:00
Dillon Beliveau	7c3af909ee	Merge branch 'dynarec_v2' into microsoft-abi	2023-07-09 00:20:47 -04:00
Dillon Beliveau	a925ba7e76	fix dangling pointer for compiler v1 and rsp	2023-07-09 00:20:24 -04:00
Dillon Beliveau	c122f9df3e	Windows support for dynarec v2 using the MS ABI	2023-07-08 18:03:29 -04:00
Dillon Beliveau	2f095b35d5	support spilling FGRs	2023-06-10 17:57:52 -07:00