1066 commits

Author	SHA1	Message	Date
Dillon Beliveau	7b5b267206	sign-extend linked PC	2020-12-08 00:33:28 -05:00
Dillon Beliveau	4a06c3b594	correctly handle FPU register accesses	2020-12-07 23:17:04 -05:00
Dillon Beliveau	25e269c722	new structure for holding FPRs	2020-12-07 22:55:11 -05:00
Dillon Beliveau	58bd80fc28	begin reworking FPU access functions	2020-12-07 22:47:00 -05:00
Dillon Beliveau	5c346cb746	DMTC1/DMFC1	2020-12-07 21:20:08 -05:00
Dillon Beliveau	356f6e97ad	compile a new block from inside the handler	2020-12-06 11:51:23 -05:00
Dillon Beliveau	38a8ffdabb	more RSP instructions	2020-12-05 22:40:19 -05:00
Dillon Beliveau	2df63bd2e3	fix tests and cleanup	2020-12-05 21:56:42 -05:00
Dillon Beliveau	ce741f13fb	Don't check every single RSP cycle if an instruction needs to be decoded	2020-12-05 20:48:04 -05:00
Dillon Beliveau	bde41c7684	rework RSP timing	2020-12-05 20:00:09 -05:00
Dillon Beliveau	b1988d9d34	fix more sanitizer-detected issues	2020-12-01 22:03:33 -05:00
Dillon Beliveau	164f6e6adb	fix some UBSan errors	2020-12-01 20:05:13 -05:00
Dillon Beliveau	b38fd7b5c4	these instructions use broadcast modifiers in VT	2020-11-29 20:54:20 -05:00
Dillon Beliveau	43ab78a908	allow reading DMA_CACHE value from RSP CP0	2020-11-29 20:54:08 -05:00
Dillon Beliveau	90270a56cf	various DMA fixes	2020-11-29 20:53:57 -05:00
Dillon Beliveau	2b2cd6f443	allow use of broadcast modifiers here	2020-11-29 20:16:06 -05:00
Dillon Beliveau	068595f29a	misaligned RSP DMA reads are only warnings	2020-11-29 12:54:21 -05:00
Dillon Beliveau	b6ce54af91	SIMD-ify lane selection where e [8, 15]	2020-11-29 12:46:09 -05:00
Dillon Beliveau	f9c3bcf190	add a warning	2020-11-29 12:04:56 -05:00
Dillon Beliveau	b63651cb82	implement DSUBU	2020-11-28 16:42:41 -05:00
Dillon Beliveau	e50c46c9c0	DSRL + DSRL32	2020-11-28 16:33:10 -05:00
Dillon Beliveau	e207ba4c8e	SIMD-ify some of the hottest RSP multiplies	2020-11-28 15:46:12 -05:00
Dillon Beliveau	956256efbc	Set flag registers to 0xFFFF instead of 1 when true	2020-11-28 15:18:46 -05:00
Dillon Beliveau	bb640818ef	separate SIMD and SISD code in rsp_vector_instructions	2020-11-28 15:06:30 -05:00
Dillon Beliveau	7b2bf54292	Release builds don't link to Capstone	2020-11-27 13:24:22 -05:00
Dillon Beliveau	fc613e621b	DADDU	2020-11-26 13:21:24 -05:00
Dillon Beliveau	01fd45594f	stub WatchLo and WatchHi	2020-11-25 13:16:35 -05:00
Dillon Beliveau	88b9b61608	comment out FR change check	2020-11-25 12:45:26 -05:00
Dillon Beliveau	ac90c99869	RSP DMA is never busy	2020-11-22 18:58:09 -05:00
Dillon Beliveau	f7516ffc5b	set CPU CP0 Config	2020-11-22 18:57:52 -05:00
Dillon Beliveau	50af228488	clean up logging	2020-11-21 13:54:53 -05:00
Dillon Beliveau	6ad4cb7d43	don't run RSP until it halts anymore	2020-11-21 13:54:29 -05:00
Dillon Beliveau	8b05868833	comments next to register names with their numbers	2020-11-01 14:26:32 -05:00
Dillon Beliveau	2c87374b88	check alignment in more places	2020-10-31 12:16:56 -04:00
Dillon Beliveau	4a352446c3	check alignment	2020-10-31 12:15:59 -04:00
Dillon Beliveau	02577b56c1	rearrange, inline	2020-10-03 21:28:32 -04:00
Dillon Beliveau	4bf05ededf	use pointers, inline	2020-10-03 20:55:03 -04:00
Dillon Beliveau	2ab1edde34	since the RSP's PC is always >>2 before it's used, just store it as its value >>2	2020-10-03 20:15:55 -04:00
Dillon Beliveau	50021b5a23	hopefully slightly faster RSP / CPU timing sync	2020-10-03 19:46:39 -04:00
Dillon Beliveau	5e21e9a46a	flush codecache when full	2020-10-03 16:55:56 -04:00
Dillon Beliveau	a284229033	vxor use vte	2020-10-03 15:07:49 -04:00
Dillon Beliveau	e655109e80	some logwarns to loginfo	2020-10-03 14:26:14 -04:00
Dillon Beliveau	088c275208	remove an unnecessary check on register access	2020-10-03 14:21:50 -04:00
Dillon Beliveau	d00106d935	fix build when log enabled	2020-10-03 14:20:31 -04:00
Dillon Beliveau	41df53bf49	cleanup logs when enabled	2020-10-02 12:19:44 -04:00
Dillon Beliveau	5808fee06b	speed up addi	2020-10-02 12:13:58 -04:00
Dillon Beliveau	b7036f3cdd	speed up BEQ	2020-10-02 12:02:09 -04:00
Dillon Beliveau	edbf24dd7a	perform all RSP steps at once without repeatedly calling	2020-10-02 10:56:36 -04:00
Dillon Beliveau	5a3db7ab61	comment	2020-10-02 10:38:21 -04:00
Dillon Beliveau	eafa8d72bc	better error messages	2020-10-02 10:36:14 -04:00