1066 commits

Author	SHA1	Message	Date
Dillon Beliveau	348aad1777	RSP timing tweaks	2020-12-24 18:06:44 -05:00
Dillon Beliveau	89f5cc32fb	cleanup a bit of code in dynarec	2020-12-24 00:31:15 -05:00
Dillon Beliveau	087509f096	remove 2 log lines	2020-12-24 00:24:15 -05:00
Dillon Beliveau	e95ce62921	JIT: make branches to self take 64 cycles in the, macro some switch statements	2020-12-23 22:41:23 -05:00
Dillon Beliveau	3b0ca0a2e1	compile TLBR	2020-12-23 21:30:05 -05:00
Dillon Beliveau	a16a3bda73	LUI with no UB	2020-12-23 19:50:11 -05:00
Dillon Beliveau	572ff6a998	tlbr seems to work, so enable it	2020-12-23 19:14:36 -05:00
Dillon Beliveau	9b5a83201c	more portable DMULT and DMULTU	2020-12-23 19:06:21 -05:00
Dillon Beliveau	91a0fdd697	mask address every time skip is added & correct length register value	2020-12-22 22:24:02 -05:00
Dillon Beliveau	b9dfa65e81	length reg in SP DMA writes as well	2020-12-22 21:58:31 -05:00
Dillon Beliveau	21d244ec02	improve mem force alignment in SP DMAs	2020-12-22 21:56:49 -05:00
Dillon Beliveau	51199cc0a0	SP DMA addresses are stored in shadow registers until the DMA runs	2020-12-22 21:46:10 -05:00
Dillon Beliveau	f28a336f5b	these are one register on hardware	2020-12-22 21:02:39 -05:00
Dillon Beliveau	533e4a4294	JIT: dmult, dsra, bltzal	2020-12-21 19:46:59 -05:00
Dillon Beliveau	73560e4a0e	BAILZERO macro	2020-12-20 17:20:51 -05:00
Dillon Beliveau	36cd6af3f8	remove logs	2020-12-20 17:17:48 -05:00
Dillon Beliveau	b54e223e1c	sra	2020-12-20 17:11:09 -05:00
Dillon Beliveau	9d640f5a95	SEAX macro	2020-12-20 16:58:08 -05:00
Dillon Beliveau	6bcdc6b081	LOADRAX/SAVERAX macros	2020-12-20 16:54:19 -05:00
Dillon Beliveau	0146ae4361	sll/srl	2020-12-20 16:40:35 -05:00
Dillon Beliveau	e0c3f1ca3c	ori/xori	2020-12-20 16:32:13 -05:00
Dillon Beliveau	e0f89a4775	reorganize	2020-12-20 16:23:31 -05:00
Dillon Beliveau	74f5a832ab	faster compiler for andi	2020-12-20 16:16:56 -05:00
Dillon Beliveau	1122d6732c	fix warning	2020-12-20 16:16:48 -05:00
Dillon Beliveau	5ab318ae72	macroin' and fixin' - (d)addi(u) shouldn't write to r0	2020-12-20 16:06:35 -05:00
Dillon Beliveau	b75d08ac59	fix addi/addiu	2020-12-20 15:52:23 -05:00
Dillon Beliveau	f0c19ba275	addi/addiu don't use handlers at all	2020-12-20 14:43:09 -05:00
Dillon Beliveau	8eae9a3dda	Function for releasing RSP semaphore	2020-12-17 23:42:58 -05:00
Dillon Beliveau	fdd544e75b	commented out definitions	2020-12-13 14:35:50 -05:00
Dillon Beliveau	55454cbad4	use MAIN_DEPENDENCY	2020-12-13 14:35:41 -05:00
Dillon Beliveau	3861a8e884	CMake updates to work with Ninja generator	2020-12-13 14:03:01 -05:00
Dillon Beliveau	20e3bb388b	better name	2020-12-13 13:50:35 -05:00
Dillon Beliveau	a20ad247ba	all macro compiles together	2020-12-13 13:23:10 -05:00
Dillon Beliveau	78ac1f50c8	better variable name to not confuse myself	2020-12-13 02:01:45 -05:00
Dillon Beliveau	7f9abd4e9d	when CP1 disabled, don't execute the instruction at all	2020-12-13 01:36:53 -05:00
Dillon Beliveau	0c64e52422	eax and notes	2020-12-13 01:36:08 -05:00
Dillon Beliveau	a56a9594e5	use correct name	2020-12-13 01:35:58 -05:00
Dillon Beliveau	6db8562720	space	2020-12-12 23:52:02 -05:00
Dillon Beliveau	b9c440659f	optionally log jit sync points	2020-12-12 22:42:44 -05:00
Dillon Beliveau	73bca68855	more macros to cut down on LOC	2020-12-12 21:54:51 -05:00
Dillon Beliveau	bbaff5596a	cut down on a bit of code duplication with some macro use	2020-12-12 21:36:31 -05:00
Dillon Beliveau	6ea375b210	fix logging compilations	2020-12-12 21:18:48 -05:00
Dillon Beliveau	a6dade9566	LFV and SFV with bug warnings	2020-12-12 18:55:03 -05:00
Dillon Beliveau	88a29fba2b	interpreter only: dmult, dsra, bltzal	2020-12-12 18:47:05 -05:00
Dillon Beliveau	3431c24ec5	DSRLV	2020-12-12 14:59:27 -05:00
Dillon Beliveau	771a609f6c	abs.s and abs.d	2020-12-08 01:46:19 -05:00
Dillon Beliveau	5bef1fb883	RSP features and stubbing to make OoT happy	2020-12-08 01:33:07 -05:00
Dillon Beliveau	4db1d5faff	don't need to check when FR changes	2020-12-08 00:59:48 -05:00
Dillon Beliveau	dcc89660c0	register access functions to own header	2020-12-08 00:59:07 -05:00
Dillon Beliveau	f09b7a3c04	checks for 64 bit addressing enabled and leaving kernel mode	2020-12-08 00:34:24 -05:00