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Author SHA1 Message Date
Dillon Beliveau
1331d482d5 support reading more PI DMA regs 2020-12-26 14:02:24 -05:00
Dillon Beliveau
a59eede65d latest version of parallel-rdp 2020-12-26 14:01:03 -05:00
Dillon Beliveau
e851332316 cleanup macros 2020-12-26 13:48:19 -05:00
Dillon Beliveau
a27a0cc9a4 faster srlv, mfhi, mthi, mflo, mtlo 2020-12-26 13:46:28 -05:00
Dillon Beliveau
0c00a8b0e4 sllv 2020-12-26 13:38:03 -05:00
Dillon Beliveau
9db558df63 faster srav 2020-12-26 13:32:23 -05:00
Dillon Beliveau
d6160bc298 just warn when byte read from N64DD 2020-12-25 23:52:08 -05:00
Dillon Beliveau
82c3791a66 RSP: sltiu, sltu 2020-12-25 22:57:19 -05:00
Dillon Beliveau
9bd908793b ldc1/sdc1/lwc1/swc1 exception handling in JIT 2020-12-25 22:43:51 -05:00
Dillon Beliveau
8cea5accbd check cp1 exceptions ldc1/sdc1/lwc1/swc1 2020-12-25 21:55:31 -05:00
Dillon Beliveau
7674bd1cac exception fixes/updates 2020-12-25 20:22:25 -05:00
Dillon Beliveau
e50539acef size assertions 2020-12-25 19:54:02 -05:00
Dillon Beliveau
b185ffa0f9 check FPU exceptions in CTC1 2020-12-25 19:13:06 -05:00
Dillon Beliveau
dfe2b2d8b8 GDB stub updates and fixes 2020-12-25 16:26:38 -05:00
Dillon Beliveau
861e04d5e6 allow switching between jit and interpreter without recompiling, debug mode forces interpreter 2020-12-25 14:43:21 -05:00
Dillon Beliveau
edc809993b don't queue audio if more than half a second is already queued 2020-12-24 18:11:33 -05:00
Dillon Beliveau
0f8a3e2ea0 write byte to SRAM in REGION_CART_2_2 2020-12-24 18:10:54 -05:00
Dillon Beliveau
348aad1777 RSP timing tweaks 2020-12-24 18:06:44 -05:00
Dillon Beliveau
f41cecd264 sram read from cart_2_1 2020-12-24 18:06:14 -05:00
Dillon Beliveau
d30a700930 update bus errors/warnings 2020-12-24 16:29:30 -05:00
Dillon Beliveau
80c5d7f076 SRAM 2020-12-24 16:25:10 -05:00
Dillon Beliveau
89f5cc32fb cleanup a bit of code in dynarec 2020-12-24 00:31:15 -05:00
Dillon Beliveau
a77cc704c2 USR2 turns logging back off 2020-12-24 00:31:02 -05:00
Dillon Beliveau
087509f096 remove 2 log lines 2020-12-24 00:24:15 -05:00
Dillon Beliveau
5583d4fe22 turn on debug logging when USR1 signal received 2020-12-24 00:06:41 -05:00
Dillon Beliveau
e95ce62921 JIT: make branches to self take 64 cycles in the, macro some switch statements 2020-12-23 22:41:23 -05:00
Dillon Beliveau
2f28a24a2d TLB translations in KSEG3 2020-12-23 21:30:13 -05:00
Dillon Beliveau
3b0ca0a2e1 compile TLBR 2020-12-23 21:30:05 -05:00
Dillon Beliveau
a16a3bda73 LUI with no UB 2020-12-23 19:50:11 -05:00
Dillon Beliveau
608ec61486 only inc count in one place 2020-12-23 19:50:06 -05:00
Dillon Beliveau
16a34d43a5 sync up with new jit timings 2020-12-23 19:49:54 -05:00
Dillon Beliveau
d73b2643c3 return zero when outside of the cart range 2020-12-23 19:15:45 -05:00
Dillon Beliveau
c9323cd564 ignore some invalid writes 2020-12-23 19:15:31 -05:00
Dillon Beliveau
572ff6a998 tlbr seems to work, so enable it 2020-12-23 19:14:36 -05:00
Dillon Beliveau
9b5a83201c more portable DMULT and DMULTU 2020-12-23 19:06:21 -05:00
Dillon Beliveau
d50742f8a2 free objects 2020-12-23 18:21:50 -05:00
Dillon Beliveau
91a0fdd697 mask address every time skip is added & correct length register value 2020-12-22 22:24:02 -05:00
Dillon Beliveau
b9dfa65e81 length reg in SP DMA writes as well 2020-12-22 21:58:31 -05:00
Dillon Beliveau
21d244ec02 improve mem force alignment in SP DMAs 2020-12-22 21:56:49 -05:00
Dillon Beliveau
51199cc0a0 SP DMA addresses are stored in shadow registers until the DMA runs 2020-12-22 21:46:10 -05:00
Dillon Beliveau
f28a336f5b these are one register on hardware 2020-12-22 21:02:39 -05:00
Dillon Beliveau
f5303cb5a8 combine cells 2020-12-22 20:29:44 -05:00
Dillon Beliveau
11bba27c24 change theme and formatting of some tables 2020-12-22 19:38:36 -05:00
Dillon Beliveau
d9cc6edc9d Every MIPS interface register documented 2020-12-22 00:53:16 -05:00
Dillon Beliveau
5f72ce7461 more MI docs 2020-12-22 00:42:41 -05:00
Dillon Beliveau
458ece5fe9 document one MI register 2020-12-22 00:14:02 -05:00
Dillon Beliveau
8e1bd59b04 back to interpreter for these tests 2020-12-21 20:33:50 -05:00
Dillon Beliveau
533e4a4294 JIT: dmult, dsra, bltzal 2020-12-21 19:46:59 -05:00
Dillon Beliveau
3ea6dde4a7 increment Count correctly in JIT 2020-12-21 19:31:46 -05:00
Dillon Beliveau
73560e4a0e BAILZERO macro 2020-12-20 17:20:51 -05:00