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Author SHA1 Message Date
Dillon Beliveau
aefd7490fb 64 bit TLB, hopefully works 2020-12-29 13:57:01 -05:00
Dillon Beliveau
139ddfbebf tlb fixes, prep for 64 bit TLB 2020-12-29 02:32:50 -05:00
Dillon Beliveau
1f8fec6dec more 64 bit accesses, detect TLB operations in 64 bit mode 2020-12-28 19:50:26 -05:00
Dillon Beliveau
0c9783a73b ll, sc 2020-12-28 19:30:06 -05:00
Dillon Beliveau
5fae26ef7b XKPHYS 2020-12-28 19:25:14 -05:00
Dillon Beliveau
babd540ef9 SCD 2020-12-28 19:25:10 -05:00
Dillon Beliveau
0845fb6ef1 lld in interpreter 2020-12-28 18:37:49 -05:00
Dillon Beliveau
854805a585 ignore writes to cart_2_1 2020-12-28 18:24:06 -05:00
Dillon Beliveau
10238640e5 64 bit version of entry_hi 2020-12-28 18:23:54 -05:00
Dillon Beliveau
75ff5f2c64 allow reads from FCR0, with a warning 2020-12-28 18:11:16 -05:00
Dillon Beliveau
946e929506 tne in interpreter 2020-12-28 18:11:16 -05:00
Dillon Beliveau
f47948369e return 0 for word reads from cart 1_3 2020-12-28 18:11:16 -05:00
Dillon Beliveau
c124a3596b context and xcontext in 64 bit mode 2020-12-28 18:11:16 -05:00
Dillon Beliveau
05a0c81088 register size fixes 2020-12-28 18:11:16 -05:00
Dillon Beliveau
1344530614 CP0 registers docs updates 2020-12-28 18:11:16 -05:00
Dillon Beliveau
d4599c16d8
Merge pull request #7 from YetAnotherEmuDev/master 
Make readme more polite
 2020-12-28 15:23:06 -05:00
YetAnotherEmuDev
706d123f72
Make readme more polite 2020-12-28 20:18:26 +00:00
Dillon Beliveau
386ad69832
Merge pull request #6 from wheremyfoodat/patch-1 
Made readme more polite
 2020-12-28 15:13:52 -05:00
wheremyfoodat
2158559ddd
Made readme more polite 2020-12-28 22:11:51 +02:00
Dillon Beliveau
38947cbcb3 update some format strings for 64 bit addressing 2020-12-28 03:16:08 -05:00
Dillon Beliveau
8e47d4c784 latest version of parallel-rdp 2020-12-28 03:00:22 -05:00
Dillon Beliveau
095ef736fc not sure why this was still here 2020-12-28 01:06:06 -05:00
Dillon Beliveau
a4304ddf36 c.un 2020-12-28 00:55:04 -05:00
Dillon Beliveau
2c25314dab fix MI_VERSION_REG 2020-12-28 00:53:59 -05:00
Dillon Beliveau
6b991b50ff probably incorrect c.ule 2020-12-28 00:32:05 -05:00
Dillon Beliveau
0a09de0365 daddiu doesn't throw overflow exceptions 2020-12-28 00:24:21 -05:00
Dillon Beliveau
8178bb7216 RDP command processing fixes 2020-12-28 00:15:56 -05:00
Dillon Beliveau
41d12a23f8 DMTC0/DMFC0 2020-12-27 17:11:37 -05:00
Dillon Beliveau
a858271685 don't crash on vsync of 0x20C 2020-12-27 12:59:38 -05:00
Dillon Beliveau
85e4fdfcad split into own method 2020-12-27 12:28:00 -05:00
Dillon Beliveau
df3b120235 mask DRAM address in SI DMA 2020-12-27 02:15:06 -05:00
Dillon Beliveau
31936ecc2a don't lower interrupts randomly 2020-12-27 02:14:57 -05:00
Dillon Beliveau
999562468c mask Count reg 2020-12-27 02:14:49 -05:00
Dillon Beliveau
24e9d8f6cc hack: write RDRAM size to 0x318 after first PI DMA 2020-12-27 02:14:28 -05:00
Dillon Beliveau
9ef2d59872 RI regs are writable, and are initialized to certain values 2020-12-27 02:08:33 -05:00
Dillon Beliveau
3cb763a164 TEQ in JIT 2020-12-27 01:36:36 -05:00
Dillon Beliveau
4b9224067c TEQ in interpreter 2020-12-27 01:18:16 -05:00
Dillon Beliveau
6a10e1c50a XKUSEG probe TLB 2020-12-26 23:18:20 -05:00
Dillon Beliveau
d69ab0cd32 64 bit addressing working 2020-12-26 23:15:03 -05:00
Dillon Beliveau
6e8bfa93fd frameworking out 64 bit addressing 2020-12-26 22:19:21 -05:00
Dillon Beliveau
b5c2b84261 NaN checks in FPU instructions 2020-12-26 19:36:17 -05:00
Dillon Beliveau
51f49b77f5 fix DIV when dividing by zero 2020-12-26 19:11:28 -05:00
Dillon Beliveau
5f7399bc7d log rom name 2020-12-26 18:35:42 -05:00
Dillon Beliveau
34fc64a2d5 CP0 fixes 2020-12-26 18:33:48 -05:00
Dillon Beliveau
4ca695c42f inc PI DRAM and CART addresses by the length 2020-12-26 17:03:52 -05:00
Dillon Beliveau
8d932033e9 set wired and context 2020-12-26 17:03:42 -05:00
Dillon Beliveau
6bedb31d1e write word to SRAM from 2_1 2020-12-26 17:01:11 -05:00
Dillon Beliveau
f6265bbee0 size asserts 2020-12-26 17:00:23 -05:00
Dillon Beliveau
e228958190 slower, but hopefully more accurate, RSP timing 2020-12-26 15:20:06 -05:00
Dillon Beliveau
13ed5844f8 tweaks and cleanup - macros 2020-12-26 15:19:54 -05:00