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1321 commits 16 branches 0 tags 17 MiB
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1321 commits

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Author SHA1 Message Date
Dillon Beliveau
5a0c7fa257 Update UI file for gtk4 2022-07-01 18:31:54 -07:00
Dillon Beliveau
690e176c33 Merge branch 'master' into gtk-frontend-2 2022-07-01 18:09:46 -07:00
Dillon Beliveau
10a4770105 Use xdg-desktop-portal with NFD 2022-07-01 18:08:12 -07:00
Dillon Beliveau
2b9c51b711 build with GTK4 2022-07-01 18:07:45 -07:00
Dillon Beliveau
7858e376d4 Merge branch 'master' into gtk-frontend-2 2022-07-01 17:56:09 -07:00
Dillon Beliveau
13b1639557 Latest version of parallel-rdp 2022-06-30 00:10:29 -07:00
Dillon Beliveau
574541b563 log a nice message when an unexpected exception is seen instead of emitting int3 2022-06-19 12:38:56 -07:00
Dillon Beliveau
287901bace JIT updates to support more exceptions, CPU TLB miss exceptions still not working 2022-06-19 01:05:29 -07:00
Dillon Beliveau
8249fd929f I guess my emulator has a name now 2022-06-18 23:52:13 -07:00
Dillon Beliveau
d4e94fc381 Fix PI DMA outside of REGION_CART_1_2 2022-06-18 23:36:24 -07:00
Dillon Beliveau
4151af79a6 Oops 2022-06-18 16:11:57 -07:00
Dillon Beliveau
50aab2ab9f cleanup exception handling code slightly 2022-06-18 16:07:53 -07:00
Dillon Beliveau
fd1d1175e8 RSP fixes in VRCP/VRCPL 2022-06-18 16:00:22 -07:00
Dillon Beliveau
1963fb2c22 RSP fixes in LTV, RSQ 2022-06-18 15:13:48 -07:00
Dillon Beliveau
a38a9a3482 cart read 8/16 bit fixes, don't use bus functions for DMAs 2022-06-18 13:46:46 -07:00
Dillon Beliveau
a746ea2948 Fix initial value of $Status 2022-06-18 12:58:10 -07:00
Dillon Beliveau
c4bfe82617 TLB fixes 2022-06-18 12:58:04 -07:00
Dillon Beliveau
749d8ade0c Exception handling fixes 2022-06-18 12:57:49 -07:00
Dillon Beliveau
70e12f5a4a Add libgtk-3-dev to dependencies 2022-06-16 20:21:45 -07:00
Dillon Beliveau
8fc5c73bb7
Remove imfilebrowser.h from contrib/imgui/CMakeLists.txt 2022-06-15 15:43:23 -07:00
Dillon Beliveau
d7e09d88ab Switch to nativefiledialog-extended for opening ROMs 2022-06-14 21:59:07 -07:00
Simone Coco
9ebc6a101d
Correct default COP0.Status value for PIF HLE (#26) 2022-06-14 14:19:19 -07:00
Dillon Beliveau
f96e2e546a this is not a 32 bit function 2022-06-12 23:10:18 -07:00
Dillon Beliveau
5c61af5795 mask entry_hi.vpn2 with page_mask on tlbwi 2022-06-12 23:09:36 -07:00
Dillon Beliveau
18da8eab9c TLB updates, properly use region when matching VPNs 2022-06-12 22:47:30 -07:00
Dillon Beliveau
799e9a51a9 Cleanup bus a bit 2022-06-12 19:53:18 -07:00
Dillon Beliveau
2c1bf778f2 fix LL, LLD, SC, SCD 2022-06-12 19:53:13 -07:00
Dillon Beliveau
c4ea8a3ed5 many small fixes, including separate memory map for user mode 2022-06-12 19:17:25 -07:00
Dillon Beliveau
dda8b64b84 minor fixes 2022-06-12 17:17:09 -07:00
Dillon Beliveau
88124bf109 test both interpreter and recompiler with cpu test roms 2022-06-12 17:16:36 -07:00
Dillon Beliveau
1086380ea6 Fix compiler warning 2022-06-12 15:58:13 -07:00
Dillon Beliveau
9a897700a2 these are correct 2022-06-12 15:56:58 -07:00
Dillon Beliveau
6fc1536c06 Comments in r4300i_handle_exception 2022-06-12 15:13:10 -07:00
Dillon Beliveau
10c8477e6b TLB exceptions in more instructions, alignment checks 2022-06-12 15:10:19 -07:00
Dillon Beliveau
6032c4662d Rework TLB functions, fix TLBP instruction 2022-06-12 14:26:07 -07:00
Dillon Beliveau
b0a5d646ba use coprocessor error 0 instead of -1 everywhere 2022-06-12 14:05:16 -07:00
Dillon Beliveau
a651fa955c fix SSV for unaligned elements 2022-06-11 20:30:32 -07:00
Dillon Beliveau
c44d4e7f64 CFC2 and CTC2 correct behavior for invalid indices 2022-06-11 19:55:13 -07:00
Dillon Beliveau
50cc6bb969 wrap RSP accesses around the end of DMEM 2022-06-11 19:36:43 -07:00
Dillon Beliveau
e6f2ad07dc Fix RSP link instructions when branch depends on value of LR 2022-06-11 19:29:37 -07:00
Dillon Beliveau
a8f6884817 fix RSP semaphore register 2022-06-11 19:21:47 -07:00
Dillon Beliveau
dcc97e864e overflow exceptions in SUB and DSUB 2022-06-11 18:47:22 -07:00
Dillon Beliveau
6977a0cfef Only raise/lower SP interrupts if only one bit is set 2022-06-11 18:32:53 -07:00
Dillon Beliveau
9c2d235c30 COP0 open bus 2022-06-11 18:30:12 -07:00
Dillon Beliveau
bc6be21d88 save reg, link, check condition to ensure LR is set correctly in BGEZALL 2022-06-11 18:20:42 -07:00
Dillon Beliveau
befc6ad8a4 Condition is checked before link 2022-06-11 17:46:41 -07:00
Dillon Beliveau
c62016aaf9 Simplify TLB registers' masking code 2022-06-11 17:42:07 -07:00
Dillon Beliveau
b6d51f07af quiet! 2022-06-11 17:17:05 -07:00
Dillon Beliveau
8576eaafde Simplify page mask masking logic 2022-06-11 16:41:50 -07:00
Dillon Beliveau
f7969a8444 replace load/store bools with bus_access_t enum 2022-06-11 16:37:00 -07:00