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Author SHA1 Message Date
Dillon Beliveau
9295edb8e1 TLB miss exceptions in LH 2022-06-11 16:28:50 -07:00
Dillon Beliveau
8d40b774ab Unused CP0 registers are a single register 2022-06-11 15:46:11 -07:00
Dillon Beliveau
47840896fe CKSEG3 2022-06-11 15:26:33 -07:00
Dillon Beliveau
b9e4a0e1e2 reserved instruction exception 2022-06-11 15:26:22 -07:00
Dillon Beliveau
1d15877f3b Support for TLB exceptions in more instructions, implement XKSEG 2022-06-11 15:12:44 -07:00
Dillon Beliveau
2bd0c760fb TLB exceptions in LL 2022-06-11 14:51:37 -07:00
Dillon Beliveau
ea2d27b447 more TLB fixes 2022-06-11 14:50:12 -07:00
Dillon Beliveau
f7400a7438 TLB fixes 2022-06-11 14:02:04 -07:00
Dillon Beliveau
92b94ecc08 TLBR reads page mask 2022-06-11 12:33:14 -07:00
Dillon Beliveau
bca5d22733 typo 2022-06-11 11:53:52 -07:00
Dillon Beliveau
5fd3da320f fix some cop0 masking and the random/wired registers 2022-06-11 10:42:50 -07:00
Dillon Beliveau
8ef29e1b8d fix test_cpu 2022-06-10 20:46:58 -07:00
Dillon Beliveau
bed9a97b7c Set prev branch flag when needed in dynarec 2022-06-10 20:46:52 -07:00
Dillon Beliveau
7ca66ccf9f Set and use branch_likely_taken flag in dynarec instead of piggybacking on branch flag 2022-06-10 20:33:07 -07:00
Dillon Beliveau
92dbfbd5a9 fix exceptions inside branch delay slots 2022-06-10 19:37:06 -07:00
Dillon Beliveau
4978d2a15a fix ai address increment 2022-06-09 22:40:37 -07:00
Dillon Beliveau
c844f9bc73 fix signed overflow check to be more reliable 2022-06-06 01:11:28 -07:00
Dillon Beliveau
59649b1601 bad_vaddr is read only 2022-06-06 00:37:40 -07:00
Dillon Beliveau
63ad3ea449 address error fixes, context/xcontext masking on writes 2022-06-05 23:59:57 -07:00
Dillon Beliveau
2da81b073e address errors in SW 2022-06-05 22:49:33 -07:00
Dillon Beliveau
f109365215 fix address error exceptions 2022-06-05 22:39:14 -07:00
Dillon Beliveau
7843efe895 fix cast 2022-06-05 16:22:06 -07:00
Dillon Beliveau
718a8ec3cf don't logalways 2022-06-05 15:31:39 -07:00
Dillon Beliveau
3ed1ec641e fix 64 bit CAUSE writes, set coprocessor_error to zero in CAUSE when the error is not with any coprocessor 2022-06-05 15:19:53 -07:00
Dillon Beliveau
da54e19af6 more TRAP instructions 2022-06-05 15:16:26 -07:00
Dillon Beliveau
fc02b2a078 TLB exceptions in SW 2022-06-05 14:28:56 -07:00
Dillon Beliveau
40afb9c887 remove asserts, implement/stub a few things to get n64-systemtest sans TLB/trap tests to run with the interpreter 2022-06-05 14:20:13 -07:00
Dillon Beliveau
68a0c186d2 latest version of tests 2022-01-16 14:37:47 -08:00
Dillon Beliveau
447c0c89a1 mask cl in srav in jit 2022-01-16 14:08:24 -08:00
Dillon Beliveau
f3cd487021 generate rs,rt,rd tests 2022-01-16 14:08:11 -08:00
Dillon Beliveau
0af9953335 fix sra/srav in jit as well 2022-01-15 17:07:49 -08:00
Dillon Beliveau
1dce496991 Support generating shift test cases, fix sra and srav 2022-01-15 17:05:22 -08:00
Dillon Beliveau
15b83f49db
Update link to compatibility list 2022-01-08 15:16:04 -05:00
Dillon Beliveau
e93e3ddabe shift rsp pc correctly when reading from the CPU 2022-01-08 11:50:34 -08:00
Dillon Beliveau
25cbbc71b1 move ERET to mips_instructions.c 2021-12-28 17:22:43 -08:00
Simone Coco
84472154f9
Fix CI on the latest commit (#22) 2021-12-28 16:15:54 -08:00
Dillon Beliveau
fc851e5f54 Maintain aspect ratio when resizing window 2021-12-19 18:02:26 -08:00
Dillon Beliveau
2d66075ec1 Compile blit shaders instead of hardcoding 2021-12-19 17:06:52 -08:00
Dillon Beliveau
6bc057f789 Remove an old obsolete TODO 2021-11-13 15:26:21 -08:00
Dillon Beliveau
2e4676b915 Merge branch 'reset-button' 2021-11-06 11:11:46 -07:00
Dillon Beliveau
f975d5bdff Add -g to debug builds 2021-11-06 11:02:25 -07:00
Dillon Beliveau
83b77683ce Reset RSP PC to 0 when resetting 2021-11-06 10:22:41 -07:00
Dillon Beliveau
1eb6a0edcc windows-debug: move all DLLs 2021-11-06 10:07:27 -07:00
Dillon Beliveau
de4f013a58 windows-debug: use SDL2d.dll 2021-11-06 09:59:22 -07:00
simuuz
053391ea2f hang at n64rom.c:162 2021-10-06 21:16:46 +02:00
simuuz
baaee9ecc6 starting work on GUI 2021-10-06 21:04:23 +02:00
Dillon Beliveau
431b6e7497
Update build.yml 2021-09-23 09:30:46 -07:00
Dillon Beliveau
cd11835311
Add Windows Debug build to CI 2021-09-23 09:21:04 -07:00
Dillon Beliveau
88efacf56f Fix compiler warnings 2021-09-20 21:08:06 -04:00
Dillon Beliveau
3284e9c570 Explicitly codify unknown SI registers 2021-09-20 21:08:00 -04:00