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Author SHA1 Message Date
Dillon Beliveau
48b2050492 fix bitfields for Windows 2022-10-04 11:11:11 -07:00
Dillon Beliveau
321fb34383 don't latch PI on ISViewer writes 2022-10-03 23:28:02 -07:00
Dillon Beliveau
0570c4ee1e replace the hack with a slightly less hacky hack 2022-09-18 14:46:06 -07:00
Dillon Beliveau
2517c5912e 16bpp textured rectangles, sorta 2022-09-18 14:29:27 -07:00
Dillon Beliveau
bc7067bac0 load_block, sorta 2022-09-18 14:28:53 -07:00
Dillon Beliveau
c8f676b63b 8bpp/16bpp tile loads 2022-09-18 12:28:19 -07:00
Dillon Beliveau
d9b4e83312 32bpp textured rectangle support in software rdp 2022-09-17 17:54:13 -07:00
Dillon Beliveau
4e2ddfa564 better self-modifying code detection: mark what addresses are code, and only invalidate a dynarec page if one of those is rewritten. 2022-09-11 19:16:04 -07:00
Dillon Beliveau
7e44ce82b7 Stall CPU when reading from PI bus latch 2022-09-10 15:34:21 -07:00
Dillon Beliveau
442ecddf83 Shorten PI bus write time 2022-09-10 15:24:50 -07:00
Dillon Beliveau
2f1217418f Emulate invalid coprocessor instructions 2022-09-10 15:16:33 -07:00
Dillon Beliveau
aa9994133f Update Linux Github Actions runner to ubuntu 22.04 2022-08-27 17:45:13 -07:00
Dillon Beliveau
3ba85444d5 fixes 2022-08-27 17:32:55 -07:00
Dillon Beliveau
66536d1501 configurable scaling 2022-08-27 15:45:43 -07:00
Dillon Beliveau
f81f96f21d key remapping support for keyboard input 2022-08-27 13:59:51 -07:00
Dillon Beliveau
aa83d37331 include stdio.h in util.h 2022-08-21 14:13:47 -07:00
Dillon Beliveau
2fa4e9a10f Use u64 in bitfield instead of bool 2022-08-20 15:47:05 -07:00
Dillon Beliveau
37803b4de5 Settings support 2022-08-20 15:45:44 -07:00
Dillon Beliveau
ced7869ca3 small amount of work on textures 2022-08-20 10:44:19 -07:00
Dillon Beliveau
1fa835ccac mark edge_coefficients_t packed 2022-08-18 23:48:26 -07:00
Dillon Beliveau
c74f30dff7 Switch to bitfields for edge coefficients 2022-08-16 20:02:07 -07:00
Dillon Beliveau
960e9627cd fix rsq 2022-08-14 18:05:16 -07:00
Dillon Beliveau
aa1b560f16 cleanup in vrsql 2022-08-14 17:30:51 -07:00
Dillon Beliveau
7a0daf47e0 cleanup in vrcph/vrsqh 2022-08-14 17:30:35 -07:00
Dillon Beliveau
b42981a08b fix vrcpl 2022-08-14 17:30:11 -07:00
Dillon Beliveau
2e7605f5e6 vrndp 2022-08-14 17:29:34 -07:00
Dillon Beliveau
c996f4ee0f vrndn 2022-08-14 17:29:00 -07:00
Dillon Beliveau
3bbc26144c vmulq 2022-08-14 17:28:42 -07:00
Dillon Beliveau
702574e322 vmacq 2022-08-14 17:28:36 -07:00
Dillon Beliveau
e764af1b8c Fix VCL 2022-08-14 16:12:24 -07:00
Dillon Beliveau
87e5ce12ac Implement all remaining undocumented RSP instructions 2022-08-14 13:54:31 -07:00
Dillon Beliveau
419bcdbb45 Implement SWV 2022-08-14 13:53:28 -07:00
Dillon Beliveau
c58f70b3c4 Fix SFV 2022-08-14 13:50:43 -07:00
Dillon Beliveau
e0dfc64119 Fix LFV 2022-08-14 13:50:09 -07:00
Dillon Beliveau
66d943e6cb DPC interface fixes 2022-08-13 16:48:08 -07:00
Dillon Beliveau
b35dc036c0 Remove mupen64plus RDP plugin support 2022-08-13 16:33:37 -07:00
Dillon Beliveau
d184004ea2 fix typo in variable name 2022-08-13 15:02:58 -07:00
Dillon Beliveau
c5811102ae Fix RSP CP0 2022-08-13 15:02:36 -07:00
Dillon Beliveau
68e6bdb039 xbus RDP display lists wrap around DMEM 2022-08-13 14:56:58 -07:00
Dillon Beliveau
078f5da439 SP MEM access edge cases 2022-08-13 14:43:26 -07:00
Dillon Beliveau
29564b540e fix SP DMAs 2022-08-13 14:15:06 -07:00
Dillon Beliveau
7f0be22338 correct PIF RAM SB edge cases 2022-08-13 12:42:59 -07:00
Dillon Beliveau
316c023897 correct PIF RAM SH edge cases 2022-08-13 11:42:42 -07:00
Dillon Beliveau
050f278487 correct latching for byte writes to cartridge 2022-08-13 11:15:40 -07:00
Dillon Beliveau
7d39b9f327 common module to hold timing information, more accurate PI DMA timings 2022-08-11 21:11:18 -07:00
Dillon Beliveau
d92359d4ad allow reading VI_STATUS_REG 2022-08-10 21:27:19 -07:00
Dillon Beliveau
9d48d5036c Correctly invalidate dynarec pages in PI DMA 2022-08-10 21:14:56 -07:00
Dillon Beliveau
a80c664c29 Implement PI bus latching 2022-08-08 22:55:31 -07:00
Dillon Beliveau
441a41fad1
Use v2 of install-qt-action 2022-08-04 09:25:02 -07:00
Dillon Beliveau
f4592cdaa2 Correct from everdrive defaults to hw defaults 2022-07-31 18:07:20 -07:00