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Author	SHA1	Message	Date
Dillon Beliveau	8fc5c73bb7	Remove imfilebrowser.h from contrib/imgui/CMakeLists.txt	2022-06-15 15:43:23 -07:00
Dillon Beliveau	d7e09d88ab	Switch to nativefiledialog-extended for opening ROMs	2022-06-14 21:59:07 -07:00
Simone Coco	9ebc6a101d	Correct default COP0.Status value for PIF HLE (#26)	2022-06-14 14:19:19 -07:00
Dillon Beliveau	f96e2e546a	this is not a 32 bit function	2022-06-12 23:10:18 -07:00
Dillon Beliveau	5c61af5795	mask entry_hi.vpn2 with page_mask on tlbwi	2022-06-12 23:09:36 -07:00
Dillon Beliveau	18da8eab9c	TLB updates, properly use region when matching VPNs	2022-06-12 22:47:30 -07:00
Dillon Beliveau	799e9a51a9	Cleanup bus a bit	2022-06-12 19:53:18 -07:00
Dillon Beliveau	2c1bf778f2	fix LL, LLD, SC, SCD	2022-06-12 19:53:13 -07:00
Dillon Beliveau	c4ea8a3ed5	many small fixes, including separate memory map for user mode	2022-06-12 19:17:25 -07:00
Dillon Beliveau	dda8b64b84	minor fixes	2022-06-12 17:17:09 -07:00
Dillon Beliveau	88124bf109	test both interpreter and recompiler with cpu test roms	2022-06-12 17:16:36 -07:00
Dillon Beliveau	1086380ea6	Fix compiler warning	2022-06-12 15:58:13 -07:00
Dillon Beliveau	9a897700a2	these are correct	2022-06-12 15:56:58 -07:00
Dillon Beliveau	6fc1536c06	Comments in r4300i_handle_exception	2022-06-12 15:13:10 -07:00
Dillon Beliveau	10c8477e6b	TLB exceptions in more instructions, alignment checks	2022-06-12 15:10:19 -07:00
Dillon Beliveau	6032c4662d	Rework TLB functions, fix TLBP instruction	2022-06-12 14:26:07 -07:00
Dillon Beliveau	b0a5d646ba	use coprocessor error 0 instead of -1 everywhere	2022-06-12 14:05:16 -07:00
Dillon Beliveau	a651fa955c	fix SSV for unaligned elements	2022-06-11 20:30:32 -07:00
Dillon Beliveau	c44d4e7f64	CFC2 and CTC2 correct behavior for invalid indices	2022-06-11 19:55:13 -07:00
Dillon Beliveau	50cc6bb969	wrap RSP accesses around the end of DMEM	2022-06-11 19:36:43 -07:00
Dillon Beliveau	e6f2ad07dc	Fix RSP link instructions when branch depends on value of LR	2022-06-11 19:29:37 -07:00
Dillon Beliveau	a8f6884817	fix RSP semaphore register	2022-06-11 19:21:47 -07:00
Dillon Beliveau	dcc97e864e	overflow exceptions in SUB and DSUB	2022-06-11 18:47:22 -07:00
Dillon Beliveau	6977a0cfef	Only raise/lower SP interrupts if only one bit is set	2022-06-11 18:32:53 -07:00
Dillon Beliveau	9c2d235c30	COP0 open bus	2022-06-11 18:30:12 -07:00
Dillon Beliveau	bc6be21d88	save reg, link, check condition to ensure LR is set correctly in BGEZALL	2022-06-11 18:20:42 -07:00
Dillon Beliveau	befc6ad8a4	Condition is checked before link	2022-06-11 17:46:41 -07:00
Dillon Beliveau	c62016aaf9	Simplify TLB registers' masking code	2022-06-11 17:42:07 -07:00
Dillon Beliveau	b6d51f07af	quiet!	2022-06-11 17:17:05 -07:00
Dillon Beliveau	8576eaafde	Simplify page mask masking logic	2022-06-11 16:41:50 -07:00
Dillon Beliveau	f7969a8444	replace load/store bools with bus_access_t enum	2022-06-11 16:37:00 -07:00
Dillon Beliveau	9295edb8e1	TLB miss exceptions in LH	2022-06-11 16:28:50 -07:00
Dillon Beliveau	8d40b774ab	Unused CP0 registers are a single register	2022-06-11 15:46:11 -07:00
Dillon Beliveau	47840896fe	CKSEG3	2022-06-11 15:26:33 -07:00
Dillon Beliveau	b9e4a0e1e2	reserved instruction exception	2022-06-11 15:26:22 -07:00
Dillon Beliveau	1d15877f3b	Support for TLB exceptions in more instructions, implement XKSEG	2022-06-11 15:12:44 -07:00
Dillon Beliveau	2bd0c760fb	TLB exceptions in LL	2022-06-11 14:51:37 -07:00
Dillon Beliveau	ea2d27b447	more TLB fixes	2022-06-11 14:50:12 -07:00
Dillon Beliveau	f7400a7438	TLB fixes	2022-06-11 14:02:04 -07:00
Dillon Beliveau	92b94ecc08	TLBR reads page mask	2022-06-11 12:33:14 -07:00
Dillon Beliveau	bca5d22733	typo	2022-06-11 11:53:52 -07:00
Dillon Beliveau	5fd3da320f	fix some cop0 masking and the random/wired registers	2022-06-11 10:42:50 -07:00
Dillon Beliveau	8ef29e1b8d	fix test_cpu	2022-06-10 20:46:58 -07:00
Dillon Beliveau	bed9a97b7c	Set prev branch flag when needed in dynarec	2022-06-10 20:46:52 -07:00
Dillon Beliveau	7ca66ccf9f	Set and use branch_likely_taken flag in dynarec instead of piggybacking on branch flag	2022-06-10 20:33:07 -07:00
Dillon Beliveau	92dbfbd5a9	fix exceptions inside branch delay slots	2022-06-10 19:37:06 -07:00
Dillon Beliveau	4978d2a15a	fix ai address increment	2022-06-09 22:40:37 -07:00
Dillon Beliveau	c844f9bc73	fix signed overflow check to be more reliable	2022-06-06 01:11:28 -07:00
Dillon Beliveau	59649b1601	bad_vaddr is read only	2022-06-06 00:37:40 -07:00
Dillon Beliveau	63ad3ea449	address error fixes, context/xcontext masking on writes	2022-06-05 23:59:57 -07:00