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Author	SHA1	Message	Date
Dillon Beliveau	5633bf4431	Rewrite register allocation algorithm	2023-02-18 14:03:35 -08:00
Dillon Beliveau	3c22197660	bltz, mult, sub	2023-02-15 23:56:11 -08:00
Dillon Beliveau	ffe720bb65	sb, blez	2023-02-14 21:59:08 -08:00
Dillon Beliveau	213fde13ca	fix less than and greater than conditions	2023-02-14 21:54:35 -08:00
Dillon Beliveau	cac306a042	breakpoints in v2 compiler	2023-02-14 21:54:07 -08:00
Dillon Beliveau	d25da46e4a	block browser improvements	2023-02-14 21:53:36 -08:00
Dillon Beliveau	ee4d709b53	cfc1, ctc1, ignore FPU instructions	2023-02-12 21:42:48 -08:00
Dillon Beliveau	2fd89ed5e5	compile set cp0 status	2023-02-12 19:37:23 -08:00
Dillon Beliveau	70b9a50e50	Distinguish valid immediates from constants in the compiler. Compile MFC0	2023-02-12 18:18:53 -08:00
Dillon Beliveau	b297034494	check registers in host emitters	2023-02-12 18:10:18 -08:00
Dillon Beliveau	1e553cebbb	DSLL, DSLL32, DSRA, DSRA32, SRA, SRAV, DSLLV, NOR, XORI, SLTI, SLTIU	2023-02-12 16:15:00 -08:00
Dillon Beliveau	4d7d9666ab	fix ir_emit_link	2023-02-12 16:13:09 -08:00
Dillon Beliveau	b9bb72eb56	DADDIU	2023-02-12 15:08:36 -08:00
Dillon Beliveau	deb17652a8	LWU and DADDI	2023-02-12 15:06:37 -08:00
Dillon Beliveau	f0025cb5b7	handle const conditions in cond block exit, fix branch likely cond negation, implement BEQL	2023-02-12 15:04:38 -08:00
Dillon Beliveau	95bf422688	don't allow binding r0 to a value	2023-02-12 14:16:06 -08:00
Dillon Beliveau	804ed3d702	fix types for VALUE_TYPE_U16	2023-02-12 14:15:56 -08:00
Dillon Beliveau	fac8224a3f	move v2_link_and_encode into a separate TU	2023-02-12 14:15:39 -08:00
Dillon Beliveau	00a407c00e	fill out entire block struct from within v2_link_and_encode	2023-02-12 13:46:31 -08:00
Dillon Beliveau	37eb87e3ad	missing_block_handler not static	2023-02-12 13:43:54 -08:00
Dillon Beliveau	9f2b323fae	not static, unique names	2023-02-12 13:35:27 -08:00
Dillon Beliveau	47ad0a4e12	updates to unimplemented cases in v2_compiler	2023-02-12 10:20:24 -08:00
Dillon Beliveau	1003a7a397	compare tool fixes	2023-02-12 10:18:27 -08:00
Dillon Beliveau	b964012d7e	subtraction fixes	2023-02-12 10:18:13 -08:00
Dillon Beliveau	ff5f223d89	missing prototype	2023-02-11 22:14:10 -08:00
Dillon Beliveau	a84394893b	bgezal	2023-02-11 22:12:40 -08:00
Dillon Beliveau	7f4cde5fab	or/xor with two variable args	2023-02-11 22:06:17 -08:00
Dillon Beliveau	3ed0f82607	XOR, SUBU, SLLV, SRLV	2023-02-11 22:01:11 -08:00
Dillon Beliveau	40a1af4201	fix various dynarec bugs	2023-02-11 21:03:25 -08:00
Dillon Beliveau	9925f84572	dynarec_compare tool	2023-02-11 21:02:21 -08:00
Dillon Beliveau	2d7886697b	preprocessor macro INSTANT_PI_DMA for debugging	2023-02-11 21:01:57 -08:00
Dillon Beliveau	decc017b84	IR multiplies, MULTU	2023-02-11 18:10:29 -08:00
Dillon Beliveau	af878c9af4	remove hardcoded reg nums	2023-02-11 15:24:35 -08:00
Dillon Beliveau	0f83d009c2	C functions to dump disassembly	2023-02-11 15:18:01 -08:00
Dillon Beliveau	50da5291ff	optimize more memory accesses to use offsets when possible	2023-02-11 15:14:38 -08:00
Dillon Beliveau	5fc06a9625	block disassembly viewer imgui	2023-02-11 14:38:50 -08:00
Dillon Beliveau	7c047b5983	Merge branch 'master' into dynarec_v2	2023-02-11 12:22:08 -08:00
Dillon Beliveau	0ca38c593b	Upgrade imgui and implot	2023-02-11 12:21:18 -08:00
Dillon Beliveau	9ebc767db3	optimize host_emit_mov_mem_reg to use an offset into N64CPU if possible	2023-02-11 11:15:06 -08:00
Dillon Beliveau	3a4b0b6d0e	Move setup-nasm action to top level	2023-02-06 09:41:36 -08:00
Dillon Beliveau	77431e74dc	Install nasm in github actions	2023-02-06 09:36:28 -08:00
Dillon Beliveau	67d777c78f	AND two variable values	2023-02-05 19:11:08 -08:00
Dillon Beliveau	0f1feb3a40	flush registers when block exited early	2023-02-05 19:01:25 -08:00
Dillon Beliveau	c99533ee8d	finish exit block early test, broken implementation	2023-02-05 18:02:43 -08:00
Dillon Beliveau	80581dd926	compiled not, start working on likely branches, start setting up unit tests for dynarec	2023-02-05 17:18:06 -08:00
Dillon Beliveau	b59d55c80b	sltu, and, or, nop cache	2023-02-05 15:28:22 -08:00
Dillon Beliveau	b9f56d6820	Logging updates	2023-02-05 15:10:43 -08:00
Dillon Beliveau	c230cff119	compiled or, not, mtc0, sanitizers not passed to nasm, reserve r12 for cpu pointer, flush regs as early as possible, const shift,	2023-02-05 15:06:36 -08:00
Dillon Beliveau	397beebe00	quiet down logs	2023-02-05 02:34:23 -08:00
Dillon Beliveau	e4c37fca2c	s8 -> fp	2023-02-05 02:18:53 -08:00