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Author	SHA1	Message	Date
Dillon Beliveau	5ae2b28272	lwc1, cp1 cvt instructions	2023-02-26 15:06:51 -08:00
Dillon Beliveau	fd39ae898d	handle consts in mov_reg_type	2023-02-26 10:40:57 -08:00
Dillon Beliveau	13fb1d6edb	remove printfs	2023-02-25 18:36:20 -08:00
Dillon Beliveau	11dbb2be39	print_ir_block in header	2023-02-25 17:50:34 -08:00
Dillon Beliveau	380a9a1977	stub FPU IR emitters	2023-02-25 17:48:59 -08:00
Dillon Beliveau	4b2d2118f1	nicer output formatting	2023-02-25 17:48:23 -08:00
Dillon Beliveau	71d406fd8c	fix warnings	2023-02-25 17:48:10 -08:00
Dillon Beliveau	94cf6af256	flush FPU registers	2023-02-25 17:30:29 -08:00
Dillon Beliveau	029996c025	fix test	2023-02-24 17:52:29 -08:00
Dillon Beliveau	b442ea894a	allocate FPU registers	2023-02-24 17:45:59 -08:00
Dillon Beliveau	8678084991	remove logfatal	2023-02-22 00:17:58 -08:00
Dillon Beliveau	40bcfe6257	oops	2023-02-20 16:54:26 -08:00
Dillon Beliveau	e69edd528c	macro for blockcache outer index	2023-02-20 16:37:24 -08:00
Dillon Beliveau	81de6a8638	fix coprocessor instruction decoding	2023-02-20 16:21:25 -08:00
Dillon Beliveau	950c557c19	print IR when difference found	2023-02-20 15:51:52 -08:00
Dillon Beliveau	c9b5ac6296	refactor interpreter to allow running the CPU for more than a single cycle at a time	2023-02-20 15:33:04 -08:00
Dillon Beliveau	5c3cd84b5e	timing slightly more accurate in n64_system_step	2023-02-20 13:14:39 -08:00
Dillon Beliveau	5034d33fd3	ldl, ldr	2023-02-20 03:20:43 -08:00
Dillon Beliveau	759f633c0f	don't expand notted consts	2023-02-20 02:47:08 -08:00
Dillon Beliveau	317b701f28	swl, swr, empty emitters for ldl, ldr, sdl, sdr	2023-02-20 02:46:06 -08:00
Dillon Beliveau	54f2e7658c	lwl/lwr	2023-02-20 02:41:00 -08:00
Dillon Beliveau	6c0ac17d8d	bltzl, bgtzl	2023-02-20 00:25:14 -08:00
Dillon Beliveau	006c99c8a4	mfc0 compare, count	2023-02-20 00:11:23 -08:00
Dillon Beliveau	8d6da6281f	bgezl	2023-02-20 00:11:12 -08:00
Dillon Beliveau	f934dc0b6c	s32 multiplies	2023-02-20 00:11:04 -08:00
Dillon Beliveau	44b71566a6	cmp reg, imm works with spilled values	2023-02-20 00:10:55 -08:00
Dillon Beliveau	b13c557498	split FPU emitters into a separate source file	2023-02-20 00:10:41 -08:00
Dillon Beliveau	f3e794a6e5	fix and reg, imm with spilled reg	2023-02-19 16:41:18 -08:00
Dillon Beliveau	d9bc1d4c7c	color coded dynarec_compare output	2023-02-19 15:16:08 -08:00
Dillon Beliveau	94e26dafcf	cleanup output of dynarec_compare	2023-02-19 14:55:26 -08:00
Dillon Beliveau	26a9404ec1	support reading EPC	2023-02-19 14:55:17 -08:00
Dillon Beliveau	19bdc159fa	add reg, reg works with spilled registers	2023-02-19 14:55:03 -08:00
Dillon Beliveau	29eb052d7a	IR_SET_PTR compiles correctly	2023-02-19 14:44:28 -08:00
Dillon Beliveau	d7d013a8a0	fix IR_SET_PTR always being optimized out	2023-02-19 14:44:03 -08:00
Dillon Beliveau	c2cabea407	eret	2023-02-19 14:27:07 -08:00
Dillon Beliveau	c9c28c60e5	dynarec_compare pick rom entrypoint as beginning of comparison	2023-02-19 04:14:12 -08:00
Dillon Beliveau	c9cca55226	replace get_mult_result with get_ptr, add mthi, mfc0 fixes and additions, more const shifts, stack alignment	2023-02-19 04:14:00 -08:00
Dillon Beliveau	a11cda4f1f	mfc0 cause, cmp reg reg for spilled regs, flush spilled regs	2023-02-19 03:36:39 -08:00
Dillon Beliveau	6c1108622d	sub const, reg	2023-02-19 03:28:08 -08:00
Dillon Beliveau	b3ff77df84	dynasm 1.4.0 -> 1.5.0	2023-02-19 03:25:23 -08:00
Dillon Beliveau	f2f115ce1f	constant propagation for logical right shift 32 bit	2023-02-18 21:25:36 -08:00
Dillon Beliveau	4cf8825581	remove CP0-specific IR instructions, add bgez, more mfc0 and mtc0 stuff	2023-02-18 21:23:09 -08:00
Dillon Beliveau	1e46858246	MTC0 stuff, ignore TLBWI	2023-02-18 21:00:11 -08:00
Dillon Beliveau	b1a66e7da4	alloc spilled register correctly	2023-02-18 20:59:42 -08:00
Dillon Beliveau	6a3a206269	oops	2023-02-18 20:41:25 -08:00
Dillon Beliveau	c0c1f1af6d	bltz should not link	2023-02-18 20:39:55 -08:00
Dillon Beliveau	4c268f80d2	dynarec_compare improvements: copy sp dmem and imem, vi timing and interrupts	2023-02-18 20:39:44 -08:00
Dillon Beliveau	1618062a91	div, more spilled reg handling	2023-02-18 19:44:39 -08:00
Dillon Beliveau	29492f76f9	register allocation fixes, mult with two variable regs, handle spilled regs in more cases	2023-02-18 17:54:30 -08:00
Dillon Beliveau	d9832061ff	pass full register allocation information to emitters, spill to stack	2023-02-18 16:30:36 -08:00