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Author SHA1 Message Date
Dillon Beliveau
5837f37998 implement ceil.l.d, ceil.w.d, floor.l.d, floor.w.d 2023-03-12 14:05:30 -07:00
Dillon Beliveau
9347c9cb61 fix 64 bit floating point register accesses 2023-03-12 13:55:45 -07:00
Dillon Beliveau
059fbf2bfa fix 32 bit floating point register accesses 2023-03-12 13:25:51 -07:00
Dillon Beliveau
72f46b462d Merge branch 'master' into dynarec_v2 2023-03-11 20:05:06 -08:00
Dillon Beliveau
89bc6ed67d mov reg_reg with both regs spilled 2023-03-11 19:51:42 -08:00
Dillon Beliveau
3154f9eeeb tlbwi/tlbp 2023-03-11 19:51:26 -08:00
Dillon Beliveau
fe2a97a80d FPU accuracy updates 2023-03-11 17:53:21 -08:00
Dillon Beliveau
665a1802fe improvements to fpu register access - not quite perfect yet 2023-03-11 16:04:22 -08:00
Dillon Beliveau
1b251a8075 check fpu exception 2023-03-11 16:04:11 -08:00
Dillon Beliveau
48d1cdae70 implement more floor instrs, implement ceil instrs 2023-03-11 14:37:29 -08:00
Dillon Beliveau
9cf8fb0c6e misaligned PC exceptions 2023-03-11 14:11:04 -08:00
Dillon Beliveau
8dadfebffa implement DSRL 2023-03-11 13:40:44 -08:00
Dillon Beliveau
a028d0e96b fix DSUBU and DSUB 2023-03-11 13:35:41 -08:00
Dillon Beliveau
dd2bc32c5d dynarec compare use shared memory for joybus devices 2023-03-11 12:46:03 -08:00
Dillon Beliveau
887a36fe2d Merge branch 'master' into dynarec_v2 2023-03-11 12:43:44 -08:00
Dillon Beliveau
ecbf11149f branch likely should only set bd flag when the branch is taken 2023-03-11 12:41:14 -08:00
Dillon Beliveau
e62fb04403 check that interpreter and jit are in sync, zero cost exceptions 2023-03-11 12:31:02 -08:00
Dillon Beliveau
3028067b66 don't print IR if it's of the wrong block 2023-03-11 11:47:13 -08:00
Dillon Beliveau
0903f616b0 pc to exception log message 2023-03-11 11:36:25 -08:00
Dillon Beliveau
117650b924 quiet down logs 2023-03-11 11:36:06 -08:00
Dillon Beliveau
a4626ed6a7 dynarec compare check cp0 2023-03-11 11:29:26 -08:00
Dillon Beliveau
1c37494031 init settings in dynarec compare, only check vi interrupts when v_current changes, allow quitting in dynarec compare 2023-03-11 11:10:45 -08:00
Dillon Beliveau
fe7b557495 disable CP1 exceptions when instant DMAs on 2023-03-11 01:08:18 -08:00
Dillon Beliveau
e6fb45b1a7 INSTANT_PI_DMA -> INSTANT_DMA 2023-03-11 01:01:57 -08:00
Dillon Beliveau
6d7ab0e4d6 fix 2023-03-11 00:49:55 -08:00
Dillon Beliveau
f1d1f5106a WIP 2023-03-10 18:49:59 -08:00
Dillon Beliveau
c91aac0bee Update error message 2023-03-07 23:18:50 -08:00
Dillon Beliveau
55dea4fcb2 remove nasm 2023-03-07 10:52:50 -08:00
Dillon Beliveau
390175bafd dynarec prologue/epilogue fixes, dangling pointer fix 2023-03-07 09:52:05 -08:00
Dillon Beliveau
35694c7842 statically allocate dynarec 2023-03-07 00:57:28 -08:00
Dillon Beliveau
c75cecb156 macro for function prologue and epilogue 2023-03-06 23:10:28 -08:00
Dillon Beliveau
870cc35c8f don't disassemble run_block 2023-03-06 23:10:13 -08:00
Dillon Beliveau
c7a6503bd9 set run block fp inside init function 2023-03-06 23:01:26 -08:00
Dillon Beliveau
336f4c21b7 Many dynarec fixes, partially to work around a strange stack corruption issue seeming to come from dynasm 2023-03-06 22:59:17 -08:00
Dillon Beliveau
bbea593d54 fix issue with loading settings 2023-03-06 22:26:49 -08:00
Dillon Beliveau
9475b6570b emit dispatcher at runtime 2023-03-06 00:01:39 -08:00
Dillon Beliveau
4521eeaa36 common min/max functions 2023-03-05 12:54:12 -08:00
Dillon Beliveau
013f04c9e4 more fpu compares 2023-03-05 12:54:12 -08:00
Dillon Beliveau
1ac424d986 64 bit multiplies and divides, spilling fixes, cp0 stuff 2023-03-05 12:54:09 -08:00
Dillon Beliveau
33cd06ba91 oops 2023-03-05 12:47:07 -08:00
Dillon Beliveau
b4a9ec4c9c handle consts more in mults and divs 2023-03-05 12:43:57 -08:00
Dillon Beliveau
0b6c26be4f cleanup 2023-03-04 17:49:10 -08:00
Dillon Beliveau
78d96889e8 CMAKE_SYSTEM_PROCESSOR is AMD64 on 64 bit Windows 2023-03-04 17:48:58 -08:00
Dillon Beliveau
8fae77d346 mkdir dynarec_v2_tests before building file into it 2023-03-04 17:46:50 -08:00
Dillon Beliveau
41bd14bd6e print cwd when test_dynarec_v2 fails to open code file 2023-03-04 17:28:09 -08:00
Dillon Beliveau
668b843f3e dadd, daddu, dsub, dsubu, spilling fixes 2023-03-04 16:46:14 -08:00
Dillon Beliveau
18f37d593b spilling fixes 2023-03-04 16:31:06 -08:00
Dillon Beliveau
b6d3f50bbc trunc double->word 2023-03-04 16:07:46 -08:00
Dillon Beliveau
1c48d6f5ab blezl, float lt compare, bc1t, bc1f, bc1fl 2023-03-04 16:02:08 -08:00
Dillon Beliveau
567da2fd81 handle spilled cond reg 2023-03-04 15:55:41 -08:00