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Author SHA1 Message Date
Dillon Beliveau
1a1ef04953 s64 multiply 2023-04-08 13:23:59 -07:00
Dillon Beliveau
59b37f750e unordered float compares, dsrlv, teq 2023-04-08 10:48:14 -07:00
Dillon Beliveau
6309dfa002 set epc, xcontext, and implement dmfc0 2023-03-27 18:04:50 -07:00
Dillon Beliveau
0d1e7cf3e7 interpreter fallback when a delay slot is on a different page from its branch 2023-03-27 18:04:08 -07:00
Dillon Beliveau
7a728522cc dmtc0 context/entryhi 2023-03-19 20:37:48 -07:00
Dillon Beliveau
25b2328ee9 check cp1 enabled 2023-03-19 15:56:46 -07:00
Dillon Beliveau
2ab8417dbc fix rom bounds checking 2023-03-19 14:40:03 -07:00
Dillon Beliveau
dcc923ec61 "sysconfig" concept for jit blocks 2023-03-19 14:39:55 -07:00
Dillon Beliveau
d6ecee8d87 more constant propagation for FPU ops 2023-03-19 13:05:51 -07:00
Dillon Beliveau
5a25741e6d improve mtc1/mfc1/dmtc1/dmfc1 2023-03-19 12:57:18 -07:00
Dillon Beliveau
42664ae697 xor spilled regs 2023-03-19 12:56:32 -07:00
Dillon Beliveau
b7cbccff3c handle spilled regs in mov_reg_imm and mult_reg_imm 2023-03-19 02:14:17 -07:00
Dillon Beliveau
f1e434b345 make check_reg a macro, so that logfatals will link to the correct line 2023-03-19 01:55:48 -07:00
Dillon Beliveau
b17ef7eb29 fix tests 2023-03-19 01:43:11 -07:00
Dillon Beliveau
bf9c0a38a1 stub float round 2023-03-19 01:37:56 -07:00
Dillon Beliveau
2013b231df dsrl32, dmfc1, dmtc1, implement float_abs_reg_reg 2023-03-19 01:29:50 -07:00
Dillon Beliveau
89847bb47c sdl, sdr, sync, ll, sc 2023-03-19 01:06:20 -07:00
Dillon Beliveau
b920127cfd clear FCR31 flag and cause in interpreter, when comparing 2023-03-18 17:30:33 -07:00
Dillon Beliveau
6932c7f383 check FCR31 in dynarec_compare 2023-03-18 17:30:14 -07:00
Dillon Beliveau
d8ba707f4a Merge branch 'master' into dynarec_v2 2023-03-18 17:19:14 -07:00
Dillon Beliveau
a9071ba5b3 dynarec_compare: cleanup IPC resources at exit 2023-03-18 16:56:02 -07:00
Dillon Beliveau
e267984840
Merge pull request #39 from Dillonb/accurate_fpu 
Accurate fpu
 2023-03-18 15:57:28 -07:00
Dillon Beliveau
bbd87af7d4 Fix FPU on Windows 2023-03-18 15:52:01 -07:00
Dillon Beliveau
1e3646457f mov.s is an alias for mov.d 2023-03-18 15:13:34 -07:00
Dillon Beliveau
2ffc72e187 sign extend when moving a 32 bit fpu reg to a gpr 2023-03-18 15:11:49 -07:00
Dillon Beliveau
28f15455b4 incomplete s64 divides 2023-03-18 14:51:12 -07:00
Dillon Beliveau
ce699fe528 Explicit error when scheduler event nodes are exhausted 2023-03-18 14:24:22 -07:00
Dillon Beliveau
29f1f0a862 Remove extra on_pi_dma_complete() call 2023-03-18 14:22:34 -07:00
Dillon Beliveau
1c136e8d9c handle spilled GPR in mov_gpr_fgr 2023-03-18 13:53:50 -07:00
Dillon Beliveau
3191f95abd float sqrt/abs/neg 2023-03-18 13:53:37 -07:00
Dillon Beliveau
ef02cf5500 when disassembling a block of guest code, print the instruction word 2023-03-18 13:52:02 -07:00
Dillon Beliveau
b2803666d1 match JIT RSP behavior in interpreter, if we are comparing the jit vs. the interpreter 2023-03-18 13:51:28 -07:00
Dillon Beliveau
ad04383c5d Fix mov reg_reg when both regs spilled 2023-03-18 13:02:38 -07:00
Dillon Beliveau
0fd0988189 Fix CVT overflow checks 2023-03-18 11:29:31 -07:00
Dillon Beliveau
b701312282 set_cause_cvt_l_d takes a double 2023-03-18 10:25:42 -07:00
Dillon Beliveau
52bf0d8048 trunc.l, round.l, ceil.l, floor.l, cvt.l wip 2023-03-13 00:05:52 -07:00
Dillon Beliveau
71ccc8d94a trunc.w, round.w, ceil.w, floor.w, cvt.w complete 2023-03-12 22:24:28 -07:00
Dillon Beliveau
8b14b3d369 updates to trunc.w, round.w, ceil.w, floor.w, cvt.w. Not quite done yet 2023-03-12 21:52:49 -07:00
Dillon Beliveau
0bcf8902a8 cvt_w_s, cvt_w_d, remove last remaining NaN asserts 2023-03-12 21:42:11 -07:00
Dillon Beliveau
2e633dac5b cvt.s.fmt, cvt.d.fmt 2023-03-12 21:12:31 -07:00
Dillon Beliveau
0a8a014443 MFC1/DMFC1/MTC1/DMTC1 preserve cause 2023-03-12 20:53:16 -07:00
Dillon Beliveau
8574cc5f70 actually, this is the behavior of all invalid FPU operations 2023-03-12 20:53:00 -07:00
Dillon Beliveau
74d546c132 DCFC1/DCTC1 throw unimplemented exception 2023-03-12 20:21:32 -07:00
Dillon Beliveau
be698f6486 all compare instructions 2023-03-12 20:21:05 -07:00
Dillon Beliveau
2e6ca46a9b exceptions and failure cases for mul/div/sqrt/abs/neg + fpu mov preserves cause 2023-03-12 18:07:46 -07:00
Dillon Beliveau
8bd11e1c05 handle FE_UNDERFLOW better 2023-03-12 18:06:37 -07:00
Dillon Beliveau
ca9bf27f56 macro for FPU ops, use for add.s/d, sub.s/d 2023-03-12 17:13:19 -07:00
Dillon Beliveau
1152761f91 exceptions and failure cases for add.d 2023-03-12 16:33:20 -07:00
Dillon Beliveau
583ea15257 exceptions and failure cases for add.s 2023-03-12 16:13:28 -07:00
Dillon Beliveau
bf820b2d96 fix FPU exceptions - unimplemented operation should always be enabled 2023-03-12 14:05:43 -07:00