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Author	SHA1	Message	Date
Dillon Beliveau	68cebca279	inline cp0_step	2020-09-20 11:26:04 -04:00
Dillon Beliveau	794bde7792	inline some decoding stuff	2020-09-20 11:22:06 -04:00
Dillon Beliveau	9149e6c12d	better name for vatopa and inline it	2020-09-20 11:17:51 -04:00
Dillon Beliveau	e91c78b683	inline some RSP branch stuff	2020-09-20 11:17:51 -04:00
Dillon Beliveau	2151c3ba41	inline some branch stuff	2020-09-20 11:17:51 -04:00
Dillon Beliveau	c6cdb60b87	cached RSP instruction decoding	2020-09-20 11:17:51 -04:00
Dillon Beliveau	5cbd800daa	disable logs without a define	2020-09-20 11:17:51 -04:00
Dillon Beliveau	a068e55732	wasd = analog stick instead of dpad	2020-09-20 11:17:51 -04:00
Dillon Beliveau	cd24e806e1	pass system to rdp_run_command	2020-09-20 11:17:51 -04:00
Dillon Beliveau	e4c3dee0d7	logtester read and process MAME logs	2020-09-20 11:17:51 -04:00
Dillon Beliveau	f0c9af2cdd	Update README.md	2020-09-19 22:41:55 -04:00
Dillon Beliveau	00ad3a2646	Update README.md	2020-09-19 22:36:04 -04:00
Dillon Beliveau	c470d20694	closer on the VRCP family of instructions, not quite there yet	2020-09-19 21:21:43 -04:00
Dillon Beliveau	079e046d41	get_vte takes a pointer	2020-09-19 20:40:44 -04:00
Dillon Beliveau	bab25d5ffa	rewrite VCH	2020-09-19 20:31:18 -04:00
Dillon Beliveau	d73ecf01de	fix LTE compare in VCL	2020-09-19 20:10:03 -04:00
Dillon Beliveau	5acc66a105	hacky hack, but don't run the RSP for a second step if it's halted	2020-09-19 14:49:56 -04:00
Dillon Beliveau	3c5af03124	fix VCR	2020-09-13 16:31:29 -04:00
Dillon Beliveau	db8ce9e6c3	fix VCL	2020-09-13 13:46:18 -04:00
Dillon Beliveau	7449bebf55	fix VNE	2020-09-13 13:26:51 -04:00
Dillon Beliveau	6159fa9a0f	fix VMOV	2020-09-13 13:07:50 -04:00
Dillon Beliveau	0312bf80c2	set vco.h to zero in VCR	2020-09-13 12:16:49 -04:00
Dillon Beliveau	e4e49cef01	split up vsvtvd macro	2020-09-13 11:54:57 -04:00
Dillon Beliveau	0b889cda77	NOR in a slightly better spot	2020-09-12 19:17:30 -04:00
Dillon Beliveau	c1dfea1716	RSP JALR and NOR	2020-09-12 17:42:33 -04:00
Dillon Beliveau	db58f828d2	add -march=native to compile flags.	2020-09-12 17:30:14 -04:00
Dillon Beliveau	9f043ded4b	fairly broken VCR	2020-09-12 17:29:25 -04:00
Dillon Beliveau	f4351b5146	no e!=0 check in vrsql	2020-09-12 15:11:32 -04:00
Dillon Beliveau	7537f5e098	VADDC lane selection	2020-09-12 15:11:21 -04:00
Dillon Beliveau	1fa7f8dded	VABS	2020-09-12 14:48:01 -04:00
Dillon Beliveau	c6baa1a83e	lane selection in VSUB and VSUBC	2020-09-12 14:42:14 -04:00
Dillon Beliveau	a5a44572ea	lane selection in VAND	2020-09-12 14:11:51 -04:00
Dillon Beliveau	d3aa85ed79	too excited here again	2020-09-12 14:11:09 -04:00
Dillon Beliveau	eaffb22e39	VMOV	2020-09-12 14:10:58 -04:00
Dillon Beliveau	9f2b2eaedb	lane selection vmrg	2020-09-12 14:04:34 -04:00
Dillon Beliveau	625c36b955	lane selection in vmrg	2020-09-12 14:04:03 -04:00
Dillon Beliveau	6365e28f5a	lane selection in vge	2020-09-12 14:01:01 -04:00
Dillon Beliveau	b0baf406f8	got a little too excited with these	2020-09-12 13:59:50 -04:00
Dillon Beliveau	30ddd2d579	handle element in VADD	2020-09-12 13:56:07 -04:00
Dillon Beliveau	b395a39224	handle element in VCH	2020-09-12 13:55:11 -04:00
Dillon Beliveau	f7244af6f0	remove some element != 0 checks where handled	2020-09-12 13:55:01 -04:00
Dillon Beliveau	92c6559472	add element != 0 checks everywhere	2020-09-12 13:51:34 -04:00
Dillon Beliveau	cae62af7a0	vte in VNXOR	2020-09-12 13:46:33 -04:00
Dillon Beliveau	36475bc68f	VNE	2020-09-12 13:46:20 -04:00
Dillon Beliveau	f9ee9952d6	VEQ	2020-09-12 13:39:22 -04:00
Dillon Beliveau	d3df05f0f0	vte-related macros	2020-09-12 13:39:15 -04:00
Dillon Beliveau	9354545c5c	rsp XORI	2020-09-12 13:18:05 -04:00
Dillon Beliveau	62ecc3318d	use VTE in VCL	2020-09-12 13:17:38 -04:00
Dillon Beliveau	192ae48fc4	unimplemented macro requires semicolon	2020-09-12 13:07:25 -04:00
Dillon Beliveau	a0e235adbc	fix STV	2020-09-12 09:36:51 -04:00