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Author SHA1 Message Date
Dillon Beliveau
4b8739f3ce don't save rax, move cpu_state type to top of file 2020-10-01 22:06:52 -04:00
Dillon Beliveau
d4f9b26142 compile cp1 2020-10-01 20:52:10 -04:00
Dillon Beliveau
ca8425b160 oops 2020-10-01 19:53:21 -04:00
Dillon Beliveau
ed2f60806a branches don't end blocks 2020-10-01 19:32:34 -04:00
Dillon Beliveau
8638091126 regimm, switch terminology to compile from emit 2020-10-01 16:31:24 -04:00
Dillon Beliveau
15bfc6c6d3 delay slots/branch likely instructions should be working now 2020-10-01 16:18:07 -04:00
Dillon Beliveau
f6212a9d15 keep track of the number of blocks run 2020-10-01 13:05:31 -04:00
Dillon Beliveau
d7faa6ba8c make sure we're at the right PC 2020-10-01 13:05:19 -04:00
Dillon Beliveau
a1f0eabbd6 emit special instructions 2020-10-01 12:36:10 -04:00
Dillon Beliveau
e7c85e344a emitters return their category, need to emit the delay slot for branch instrs 2020-10-01 12:25:38 -04:00
Dillon Beliveau
0fc6591fa9 less redundant log messages 2020-10-01 12:01:03 -04:00
Dillon Beliveau
48a9510744 builds on MacOS 2020-10-01 10:15:00 -04:00
Dillon Beliveau
d83cb1f1c1 attempting to fix blocks 2020-10-01 09:30:41 -04:00
Dillon Beliveau
cbbed8da66 emit cp0 instructions 2020-09-29 20:25:21 -04:00
Dillon Beliveau
39e2435550 compile all basic instructions 2020-09-29 20:20:16 -04:00
Dillon Beliveau
e81fbd1bac reorganize a bit 2020-09-29 19:55:58 -04:00
Dillon Beliveau
6a50589921 correct block length 2020-09-29 19:52:33 -04:00
Dillon Beliveau
4d39684159 framework for multiple instructions per block 2020-09-29 19:50:44 -04:00
Dillon Beliveau
aebf4ca4f4 cleanup, 128MiB code cache 2020-09-28 23:29:20 -04:00
Dillon Beliveau
e164db7caa fix dynarec 2020-09-28 22:50:50 -04:00
Dillon Beliveau
b008630ccf cached interpreter works, exceptions still broken 2020-09-26 19:35:53 -04:00
Dillon Beliveau
9702287e7b cached interpreter can generate a block and call it 2020-09-26 16:50:47 -04:00
Dillon Beliveau
eb5197c441 wire in dynasm 2020-09-26 01:01:47 -04:00
Dillon Beliveau
5b2d33cf9c beginnings of a dynarec/cached interpreter 2020-09-25 22:39:26 -04:00
Dillon Beliveau
272d1837d6 remove instruction type enum requirement 2020-09-24 19:40:03 -04:00
Dillon Beliveau
5670c28aa1 don't use instruction type enum in RSP, use function pointers 2020-09-24 19:27:48 -04:00
Dillon Beliveau
38e845db7b this is compiling as an if/else chain anyways, so make it a little less complex and reorder it in order of most likely branch to be hit 2020-09-24 18:21:50 -04:00
Dillon Beliveau
bbe1bca189 no separate function for cp0_step, don't calculate CP0 random 2020-09-23 23:16:53 -04:00
Dillon Beliveau
e1d2b824ed optimizing 2020-09-23 22:51:40 -04:00
Dillon Beliveau
6bb62ddbfa changes to CPU/RSP syncing 2020-09-23 22:28:39 -04:00
Dillon Beliveau
ae99c546f7 memcpy to read words from byte array 2020-09-23 22:28:07 -04:00
Dillon Beliveau
b9d718fd61 remove some indirection around reading words 2020-09-23 22:27:18 -04:00
Dillon Beliveau
a729d71dee don't check this in debug mode 2020-09-23 21:16:51 -04:00
Dillon Beliveau
78e6d9fb97 little bit faster virtual to physical translation, I hope 2020-09-23 21:16:42 -04:00
Dillon Beliveau
57052d717f Stop checking logs in RSP tests 2020-09-23 00:59:27 -04:00
Dillon Beliveau
d98b15150f remove double definition 2020-09-23 00:54:02 -04:00
Dillon Beliveau
4325daec02 vsync back on, better cycles_per_instr support 2020-09-23 00:44:39 -04:00
Dillon Beliveau
9a3b118bbd turn on parallel for angrylion 2020-09-23 00:25:20 -04:00
Dillon Beliveau
e4b694e7ec N64_DEBUG_MODE define, use two PCs in the RSP as well 2020-09-23 00:25:12 -04:00
Dillon Beliveau
28056f1f2a r4300i: change to a double-pc method of handling branch delay 2020-09-23 00:05:23 -04:00
Dillon Beliveau
a65a507692 pc is a word 2020-09-22 22:31:00 -04:00
Dillon Beliveau
50b86aea73 don't check verbosity unless logging enabled 2020-09-22 22:30:54 -04:00
Dillon Beliveau
2eb9a59e35 die on cp0 r7 write 2020-09-22 21:01:45 -04:00
Dillon Beliveau
c683e694db angrylion calls both VidExt_GL_SwapBuffers and our RenderingCallback, so just push a frame from one place. 2020-09-22 21:01:08 -04:00
Dillon Beliveau
579fb3c83b 1cpi, 1 rsp instruction per cpu instruction (incorrect, but it'll do for now) 2020-09-22 20:58:25 -04:00
Dillon Beliveau
9a0a74dd67 count is a dword and inc'd/checked differently than I thought 2020-09-22 20:58:07 -04:00
Dillon Beliveau
2e4b2749df no VSYNC 2020-09-20 15:03:10 -04:00
Dillon Beliveau
fb592a1d99 timing changes 2020-09-20 15:03:05 -04:00
Dillon Beliveau
8b1feaf5b2 map z trigger 2020-09-20 15:02:55 -04:00
Dillon Beliveau
bd2ab7571b inline RSP decoding stuff 2020-09-20 12:46:04 -04:00