Commit graph

12 commits

Author SHA1 Message Date
Tyler J. Stachecki
bb41f7208e Implement mapped SRAM accesses. 2016-03-20 15:18:17 -04:00
Tyler J. Stachecki
a4f0d7245a bus: Reduce number of MMIO address mappings. 2016-01-27 03:13:57 -05:00
Mike Ryan
e48d982023 flashram: implement FlashRAM in PI, with mapped reads 2016-01-25 20:09:46 -08:00
Derek "Turtle" Roe
8b89df2fdc See long description
Replaced all references to simulation with emulation
Updated copyright year
Updated .gitignore to reduce chances of random files being uploaded to
the repo
Added .gitattributes to normalize all text files, and to ignore binary
files (which includes the logo and the NEC PDF)
2015-07-01 18:44:21 -05:00
Tyler Stachecki
10fc81d7a3 Start filling in lots of 64DD implementation.
Also, fix a few bugs in the past two commits.
2015-01-06 22:21:00 -05:00
Tyler Stachecki
c6729b8dcc Add C2, data sector and MS RAM mappings for 64DD. 2015-01-06 14:29:16 -05:00
Tyler Stachecki
cc3aff976c Add 64DD mappings and a controller. 2015-01-06 14:07:45 -05:00
Tyler Stachecki
538e344442 Add a -nointerface switch, remove spare '\t's. 2014-11-11 17:21:25 -05:00
Tyler Stachecki
e89f054674 Optimize extremely aggressively.
Tell GCC to optimize cold functions for size and stash them away in
a separate part of the binary. Put the simulate core, meanwhile, on
the hot path. Also, bump optimization to -O3 as we can now "afford"
to do so.
2014-11-05 08:39:47 -05:00
Tyler Stachecki
08439c0f5f Remove some calls to malloc(...). 2014-11-01 16:59:12 -04:00
Tyler Stachecki
25a6ae8431 Mask bus writes to requested type, etc. 2014-04-18 13:34:23 -04:00
Tyler Stachecki
ca81cc95f5 Start executing PIF ROM. 2014-03-09 22:38:47 -04:00