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bus: Reduce number of MMIO address mappings.

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This commit is contained in:
Tyler J. Stachecki 2016-01-27 02:31:50 -05:00
parent b4a68338e1
commit a4f0d7245a
7 changed files with 83 additions and 71 deletions
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44
bus/address.h
View file

@ -15,30 +15,35 @@
#define AI_REGS_BASE_ADDRESS 0x04500000
#define AI_REGS_ADDRESS_LEN 0x00000018
// DD C2 sector buffer.
#define DD_C2S_BUFFER_ADDRESS 0x05000000
#define DD_C2S_BUFFER_LEN 0x00000400
// DD C2S and DS buffers, DD interface regs, and DD microsequencer RAM.
// These entries are all stuffed into one to reduce memorymap entries.
#define DD_REGS_BASE_ADDRESS 0x05000500
#define DD_MS_RAM_ADDRESS 0x05000580
// DD data sector buffer.
#define DD_DS_BUFFER_ADDRESS 0x05000400
#define DD_C2S_BUFFER_LEN 0x00000400
#define DD_DS_BUFFER_LEN 0x00000100
#define DD_REGS_ADDRESS_LEN 0x00000080
#define DD_MS_RAM_LEN 0x00000040
#define DD_CONTROLLER_ADDRESS 0x05000000
#define DD_CONTROLLER_LEN (DD_C2S_BUFFER_LEN + \
DD_DS_BUFFER_LEN + \
DD_REGS_ADDRESS_LEN + \
DD_MS_RAM_LEN \
)
// DD IPL ROM.
#define DD_IPL_ROM_ADDRESS 0x06000000
#define DD_IPL_ROM_LEN 0x00400000
// DD microsequencer RAM.
#define DD_MS_RAM_ADDRESS 0x05000580
#define DD_MS_RAM_LEN 0x00000040
// DD interface registers.
#define DD_REGS_BASE_ADDRESS 0x05000500
#define DD_REGS_ADDRESS_LEN 0x0000004C
// Display processor registers.
#define DP_REGS_BASE_ADDRESS 0x04100000
#define DP_REGS_ADDRESS_LEN 0x00000020
// FlashRAM registers.
#define FLASHRAM_BASE_ADDRESS 0x08000000
#define FLASHRAM_ADDRESS_LEN 0x00010004 // FIXME is this accurate?
// MIPS interface registers.
#define MI_REGS_BASE_ADDRESS 0x04300000
#define MI_REGS_ADDRESS_LEN 0x00000010
@ -47,13 +52,15 @@
#define PI_REGS_BASE_ADDRESS 0x04600000
#define PI_REGS_ADDRESS_LEN 0x00100000
// Peripheral interface RAM.
// Peripheral interface RAM and ROM.
#define PIF_ROM_BASE_ADDRESS 0x1FC00000
#define PIF_ROM_ADDRESS_LEN 0x000007C0
#define PIF_RAM_BASE_ADDRESS 0x1FC007C0
#define PIF_RAM_ADDRESS_LEN 0x00000040
// Peripheral interface ROM.
#define PIF_ROM_BASE_ADDRESS 0x1FC00000
#define PIF_ROM_ADDRESS_LEN 0x000007C0
#define PIF_BASE_ADDRESS PIF_ROM_BASE_ADDRESS
#define PIF_ADDRESS_LEN (PIF_ROM_ADDRESS_LEN + PIF_RAM_ADDRESS_LEN)
// Physical memory.
#define RDRAM_BASE_ADDRESS 0x00000000
@ -91,8 +98,5 @@
#define VI_REGS_BASE_ADDRESS 0x04400000
#define VI_REGS_ADDRESS_LEN 0x00000038
#define FLASHRAM_BASE_ADDRESS 0x08000000
#define FLASHRAM_ADDRESS_LEN 0x00010004 // FIXME is this accurate?
#endif

13
bus/controller.c
View file

@ -25,7 +25,7 @@
#include "vr4300/cpu.h"
#include "vr4300/interface.h"
#define NUM_MAPPINGS 20
#define NUM_MAPPINGS 16
struct bus_controller_mapping {
memory_rd_function read;
@ -40,7 +40,6 @@ int bus_init(struct bus_controller *bus) {
static const struct bus_controller_mapping mappings[NUM_MAPPINGS] = {
{read_ai_regs, write_ai_regs, AI_REGS_BASE_ADDRESS, AI_REGS_ADDRESS_LEN},
{read_dd_regs, write_dd_regs, DD_REGS_BASE_ADDRESS, DD_REGS_ADDRESS_LEN},
{read_dp_regs, write_dp_regs, DP_REGS_BASE_ADDRESS, DP_REGS_ADDRESS_LEN},
{read_mi_regs, write_mi_regs, MI_REGS_BASE_ADDRESS, MI_REGS_ADDRESS_LEN},
{read_pi_regs, write_pi_regs, PI_REGS_BASE_ADDRESS, PI_REGS_ADDRESS_LEN},
@ -51,12 +50,9 @@ int bus_init(struct bus_controller *bus) {
{read_cart_rom, write_cart_rom, ROM_CART_BASE_ADDRESS, ROM_CART_ADDRESS_LEN},
{read_flashram, write_flashram, FLASHRAM_BASE_ADDRESS, FLASHRAM_ADDRESS_LEN},
{read_dd_c2s_buffer, write_dd_c2s_buffer, DD_C2S_BUFFER_ADDRESS, DD_C2S_BUFFER_LEN},
{read_dd_ds_buffer, write_dd_ds_buffer, DD_DS_BUFFER_ADDRESS, DD_DS_BUFFER_LEN},
{read_dd_ms_ram, write_dd_ms_ram, DD_MS_RAM_ADDRESS, DD_MS_RAM_LEN},
{read_dd_controller, write_dd_controller, DD_CONTROLLER_ADDRESS, DD_CONTROLLER_LEN},
{read_dd_ipl_rom, write_dd_ipl_rom, DD_IPL_ROM_ADDRESS, DD_IPL_ROM_LEN},
{read_pif_ram, write_pif_ram, PIF_RAM_BASE_ADDRESS, PIF_RAM_ADDRESS_LEN},
{read_pif_rom, write_pif_rom, PIF_ROM_BASE_ADDRESS, PIF_ROM_ADDRESS_LEN},
{read_pif_rom_and_ram, write_pif_rom_and_ram, PIF_BASE_ADDRESS, PIF_ADDRESS_LEN},
{read_rdram_regs, write_rdram_regs, RDRAM_REGS_BASE_ADDRESS, RDRAM_REGS_ADDRESS_LEN},
{read_sp_regs2, write_sp_regs2, SP_REGS2_BASE_ADDRESS, SP_REGS2_ADDRESS_LEN},
{read_sp_mem, write_sp_mem, SP_MEM_BASE_ADDRESS, SP_MEM_ADDRESS_LEN},
@ -64,7 +60,6 @@ int bus_init(struct bus_controller *bus) {
void *instances[NUM_MAPPINGS] = {
bus->ai,
bus->dd,
bus->rdp,
bus->vr4300,
bus->pi,
@ -77,8 +72,6 @@ int bus_init(struct bus_controller *bus) {
bus->pi,
bus->dd,
bus->dd,
bus->dd,
bus->dd,
bus->si,
bus->si,
bus->ri,

2
bus/memorymap.h
View file

@ -42,7 +42,7 @@ struct memory_map_node {
};
struct memory_map {
struct memory_map_node mappings[22];
struct memory_map_node mappings[18];
struct memory_map_node *nil;
struct memory_map_node *root;

62
dd/controller.c
View file

@ -34,6 +34,12 @@ const char *dd_register_mnemonics[NUM_DD_REGISTERS] = {
};
#endif
static int read_dd_regs(void *opaque, uint32_t address, uint32_t *word);
static int write_dd_regs(void *opaque, uint32_t address, uint32_t word, uint32_t dqm);
static int read_dd_ms_ram(void *opaque, uint32_t address, uint32_t *word);
static int write_dd_ms_ram(void *opaque, uint32_t address, uint32_t word, uint32_t dqm);
// ASIC_CMD_STATUS flags.
#define DD_CMD_NOOP 0x00000000U
#define DD_CMD_SEEK_READ 0x00010001U
@ -108,6 +114,11 @@ int read_dd_regs(void *opaque, uint32_t address, uint32_t *word) {
unsigned offset = address - DD_REGS_BASE_ADDRESS;
enum dd_register reg = (offset >> 2);
// XXX: There is some 'extra' space in the DD register MMIO
// space that gets mapped here in order to make the memory
// map a little more efficient. It shouldn't impact anything,
// but be wary.
*word = dd->regs[reg];
debug_mmio_read(dd, dd_register_mnemonics[reg], *word);
return 0;
@ -119,6 +130,11 @@ int write_dd_regs(void *opaque, uint32_t address, uint32_t word, uint32_t dqm) {
unsigned offset = address - DD_REGS_BASE_ADDRESS;
enum dd_register reg = (offset >> 2);
// XXX: There is some 'extra' space in the DD register MMIO
// space that gets mapped here in order to make the memory
// map a little more efficient. It shouldn't impact anything,
// but be wary.
debug_mmio_write(dd, dd_register_mnemonics[reg], word, dqm);
// Command register written: do something.
@ -195,39 +211,37 @@ int write_dd_ipl_rom(void *opaque, uint32_t address, uint32_t word, uint32_t dqm
return 0;
}
// Reads a word from the DD C2S buffer.
int read_dd_c2s_buffer(void *opaque, uint32_t address, uint32_t *word) {
// Reads a word from the DD C2S/DS buffer.
int read_dd_controller(void *opaque, uint32_t address, uint32_t *word) {
struct dd_controller *dd = (struct dd_controller *) opaque;
unsigned offset = address - DD_C2S_BUFFER_ADDRESS;
unsigned offset = address - DD_CONTROLLER_ADDRESS;
debug_mmio_read(dd, "DD_C2S_BUFFER", *word);
// XXX: Hack to reduce memorymap entries.
if (address >= DD_MS_RAM_ADDRESS)
return read_dd_ms_ram(opaque, address, word);
else if (address >= DD_REGS_BASE_ADDRESS)
return read_dd_regs(opaque, address, word);
// XXX: Normal CS2/DS buffer access begins here.
debug_mmio_read(dd, "DD_C2S/DS_BUFFER", *word);
return 0;
}
// Writes a word to the DD C2S BUFFER.
int write_dd_c2s_buffer(void *opaque, uint32_t address, uint32_t word, uint32_t dqm) {
// Writes a word to the DD C2S/DS BUFFER.
int write_dd_controller(void *opaque, uint32_t address, uint32_t word, uint32_t dqm) {
struct dd_controller *dd = (struct dd_controller *) opaque;
unsigned offset = address - DD_C2S_BUFFER_ADDRESS;
unsigned offset = address - DD_CONTROLLER_ADDRESS;
debug_mmio_write(dd, "DD_C2S_BUFFER", word, dqm);
return 0;
}
// XXX: Hack to reduce memorymap entries.
if (address >= DD_MS_RAM_ADDRESS)
return write_dd_ms_ram(opaque, address, word, dqm);
// Reads a word from the DD DS buffer.
int read_dd_ds_buffer(void *opaque, uint32_t address, uint32_t *word) {
struct dd_controller *dd = (struct dd_controller *) opaque;
unsigned offset = address - DD_DS_BUFFER_ADDRESS;
else if (address >= DD_REGS_BASE_ADDRESS)
return write_dd_regs(opaque, address, word, dqm);
debug_mmio_read(dd, "DD_DS_BUFFER", *word);
return 0;
}
// Writes a word to the DD DS BUFFER.
int write_dd_ds_buffer(void *opaque, uint32_t address, uint32_t word, uint32_t dqm) {
struct dd_controller *dd = (struct dd_controller *) opaque;
unsigned offset = address - DD_DS_BUFFER_ADDRESS;
debug_mmio_write(dd, "DD_DS_BUFFER", word, dqm);
// XXX: Normal CS2/DS buffer access begins here.
debug_mmio_write(dd, "DD_C2S/DS_BUFFER", word, dqm);
return 0;
}

13
dd/controller.h
View file

@ -32,7 +32,7 @@ struct dd_controller {
const uint8_t *rom;
size_t rom_size;
uint32_t regs[NUM_DD_REGISTERS];
uint32_t regs[DD_REGS_ADDRESS_LEN / 4];
uint8_t c2s_buffer[DD_C2S_BUFFER_LEN];
uint8_t ds_buffer[DD_DS_BUFFER_LEN];
uint8_t ms_ram[DD_MS_RAM_LEN];
@ -41,18 +41,11 @@ struct dd_controller {
cen64_cold int dd_init(struct dd_controller *dd, struct bus_controller *bus,
const uint8_t *ddipl, const uint8_t *ddrom, size_t ddrom_size);
int read_dd_regs(void *opaque, uint32_t address, uint32_t *word);
int write_dd_regs(void *opaque, uint32_t address, uint32_t word, uint32_t dqm);
int read_dd_ipl_rom(void *opaque, uint32_t address, uint32_t *word);
int write_dd_ipl_rom(void *opaque, uint32_t address, uint32_t word, uint32_t dqm);
int read_dd_c2s_buffer(void *opaque, uint32_t address, uint32_t *word);
int write_dd_c2s_buffer(void *opaque, uint32_t address, uint32_t word, uint32_t dqm);
int read_dd_ds_buffer(void *opaque, uint32_t address, uint32_t *word);
int write_dd_ds_buffer(void *opaque, uint32_t address, uint32_t word, uint32_t dqm);
int read_dd_ms_ram(void *opaque, uint32_t address, uint32_t *word);
int write_dd_ms_ram(void *opaque, uint32_t address, uint32_t word, uint32_t dqm);
int read_dd_controller(void *opaque, uint32_t address, uint32_t *word);
int write_dd_controller(void *opaque, uint32_t address, uint32_t word, uint32_t dqm);
#endif

13
si/controller.c
View file

@ -28,6 +28,9 @@ const char *si_register_mnemonics[NUM_SI_REGISTERS] = {
};
#endif
static int read_pif_ram(void *opaque, uint32_t address, uint32_t *word);
static int write_pif_ram(void *opaque, uint32_t address, uint32_t word, uint32_t dqm);
static void pif_process(struct si_controller *si);
static int pif_perform_command(struct si_controller *si, unsigned channel,
uint8_t *send_buf, uint8_t send_bytes, uint8_t *recv_buf, uint8_t recv_bytes);
@ -285,10 +288,13 @@ int read_pif_ram(void *opaque, uint32_t address, uint32_t *word) {
}
// Reads a word from PIF ROM.
int read_pif_rom(void *opaque, uint32_t address, uint32_t *word) {
int read_pif_rom_and_ram(void *opaque, uint32_t address, uint32_t *word) {
uint32_t offset = address - PIF_ROM_BASE_ADDRESS;
struct si_controller *si = (struct si_controller*) opaque;
if (address >= PIF_RAM_BASE_ADDRESS)
return read_pif_ram(opaque, address, word);
memcpy(word, si->rom + offset, sizeof(*word));
*word = byteswap_32(*word);
return 0;
@ -322,7 +328,10 @@ int write_pif_ram(void *opaque, uint32_t address, uint32_t word, uint32_t dqm) {
}
// Writes a word to PIF ROM.
int write_pif_rom(void *opaque, uint32_t address, uint32_t word, uint32_t dqm) {
int write_pif_rom_and_ram(void *opaque, uint32_t address, uint32_t word, uint32_t dqm) {
if (address >= PIF_RAM_BASE_ADDRESS)
return write_pif_ram(opaque, address, word, dqm);
assert(0 && "Attempt to write to PIF ROM.");
return 0;
}

7
si/controller.h
View file

@ -49,11 +49,10 @@ cen64_cold int si_init(struct si_controller *si, struct bus_controller *bus,
const uint8_t *eeprom, size_t eeprom_size,
const struct controller *controller);
int read_pif_ram(void *opaque, uint32_t address, uint32_t *word);
int read_pif_rom(void *opaque, uint32_t address, uint32_t *word);
int read_pif_rom_and_ram(void *opaque, uint32_t address, uint32_t *word);
int write_pif_rom_and_ram(void *opaque, uint32_t address, uint32_t word, uint32_t dqm);
int read_si_regs(void *opaque, uint32_t address, uint32_t *word);
int write_pif_ram(void *opaque, uint32_t address, uint32_t word, uint32_t dqm);
int write_pif_rom(void *opaque, uint32_t address, uint32_t word, uint32_t dqm);
int write_si_regs(void *opaque, uint32_t address, uint32_t word, uint32_t dqm);
#endif