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Author SHA1 Message Date
Tyler Stachecki
3c2e806ef3 Debugger: Refactor and memory view address fix. 2015-01-16 22:25:16 -05:00
Tyler Stachecki
34150fe797 Debugger: Start populating views with UI elements. 2015-01-16 17:17:26 -05:00
Tyler Stachecki
9e5c02c3e7 Debugger: Add boilerplate stuff. 2015-01-15 16:38:55 -05:00
Tyler Stachecki
b6df46c51d Cleanup/organize some CMake stuff. 2015-01-14 11:38:48 -05:00
Tyler Stachecki
4e286507f0 Remove a build artifact from the last commit. 2015-01-14 11:23:03 -05:00
Tyler Stachecki
aa9227ac48 Debugger: Initial commit. 2015-01-14 11:18:09 -05:00
torque
8471c823f6 Build: find correct OpenGL on OS X. 
cmake needs to find the OpenGL corresponding to XQuartz, not the system
framework. Introduce a custom find module to do this on OS X.

Also define _DARWIN_C_SOURCE on OS X, which is needed for signal.h to
not throw an error.
 2015-01-14 10:06:04 -05:00
Tyler Stachecki
4b77d3ed61 RSP: Fix opcode cache bug. 2015-01-13 18:02:01 -05:00
Tyler Stachecki
e073637d33 Add some temporary hacks to the PI and UB fixes. 2015-01-13 18:01:49 -05:00
Augustin Cavalier
4d206cb0cd *_window: include gl_window.h 2015-01-13 14:10:44 -05:00
Augustin Cavalier
80a30663a5 os: move MAX_FRAME_DATA_SIZE to gl_window.h 2015-01-13 13:41:02 -05:00
Augustin Cavalier
bd04fc24fc keycodes: remove duplicate definition of CEN64_KEY_PERIOD. 2015-01-13 12:22:41 -05:00
Augustin Cavalier
022e628fc5 OS: move glx_window & keycodes to an "x11" subdir. 
UNIX does not imply X11.
 2015-01-13 11:35:56 -05:00
Augustin Cavalier
c2c8b7efce CMakeLists.txt: style fix. No functional change. 
That is, no functional change unless you have UNIX and WIN32 defined
at the same time. But who does that?!
 2015-01-13 11:14:02 -05:00
Tyler Stachecki
75a90282c5 Fix OS X builds, courtesy of dtm. 2015-01-12 21:40:18 -05:00
Tyler Stachecki
59f48b9637 VR4300: Optimize load/store instructions. 2015-01-10 16:21:34 -05:00
Tyler Stachecki
db7ef1cbb3 VR4300: Cache read/write optimizations. 2015-01-10 14:17:32 -05:00
Tyler Stachecki
6c94bb8c0b VR4300: Memory system optimizations. 2015-01-10 14:17:22 -05:00
Tyler Stachecki
acd03ec4c6 RSP: Add an opcode cache for performance. 2015-01-09 23:22:39 -05:00
Tyler Stachecki
2c94219a9b RSP: Fix scalar load-use stall. 2015-01-09 23:22:32 -05:00
Tyler Stachecki
79b02e4702 RSP: Optimize memory requests slightly. 2015-01-09 23:22:26 -05:00
Tyler Stachecki
28196d2076 RSP: Optimize decoder/stall checks slightly. 2015-01-09 23:22:20 -05:00
Tyler Stachecki
3e299ed764 Allow PI DMAs past 32MiB cart range. 2015-01-09 12:23:39 -05:00
Tyler Stachecki
5ec667b3d6 Fix a bug in Windows builds in the last commit. 2015-01-08 14:37:54 -05:00
Tyler Stachecki
56426bb6ef Make the cart ROM an optional argument. 2015-01-08 12:17:26 -05:00
Tyler Stachecki
67fca6c47f Add -ddrom to the command line. 2015-01-08 12:17:17 -05:00
Tyler Stachecki
321cf584f0 Remove some hacks from the RSP pipeline. 2015-01-08 12:17:06 -05:00
Tyler Stachecki
88a3ea5646 Add (unoptimized) SSE2 support. 2015-01-07 17:37:24 -05:00
John Paul Adrian Glaubitz
5e16526958 Fix name mismatches of 'srcp' parameter in rsp_vect_load_and_shuffle_operand. 
Signed-off-by: Tyler Stachecki <tstache1@binghamton.edu>
 2015-01-07 09:41:43 -05:00
John Paul Adrian Glaubitz
bdbfaf785b Fix dereferencing of 'word' parameter in write_dd_regs. 
Signed-off-by: Tyler Stachecki <tstache1@binghamton.edu>
 2015-01-07 09:39:26 -05:00
Tyler Stachecki
58373a30a2 Fix a batch of mistakes in the last commit. 2015-01-06 22:21:23 -05:00
Tyler Stachecki
ce34ff04c4 Prevent 64DD thread from crashing. 
RTC adjustment works and communication between the 64DD is
now present, but we don't actually save the RTC settings.
 2015-01-06 22:21:09 -05:00
Tyler Stachecki
10fc81d7a3 Start filling in lots of 64DD implementation. 
Also, fix a few bugs in the past two commits.
 2015-01-06 22:21:00 -05:00
Tyler Stachecki
c6729b8dcc Add C2, data sector and MS RAM mappings for 64DD. 2015-01-06 14:29:16 -05:00
Tyler Stachecki
cc3aff976c Add 64DD mappings and a controller. 2015-01-06 14:07:45 -05:00
Tyler Stachecki
028d8e673d Decoder optimization: drastically reduce size. 2015-01-06 11:39:36 -05:00
Tyler Stachecki
efc4e38793 Remove an old, unused function. 2015-01-06 02:18:49 -05:00
Tyler Stachecki
e63f8b08e3 Perform some really clever branch folding. 
Fold all the integer loads and stores into one code path.
 2015-01-06 02:18:31 -05:00
Tyler Stachecki
ec3748f0c2 Trim off a few hundred bytes of code. 2015-01-05 22:59:52 -05:00
Tyler Stachecki
9aba20b423 Change the device subsystem cycle order. 
We can eek out a little more performance by preferentially
cycles devices in a certain order.
 2015-01-05 22:12:56 -05:00
Tyler Stachecki
c7a4a43242 Same as the last commit, but with the RSP. 2015-01-05 22:12:44 -05:00
Tyler Stachecki
57b026450c Mark LDI (interlocks) as unlikely. 
MIPS compilers of the time optimized this out very aggressively as
they waste cycles and there's generally other instructions you can
toss in the load delay slot, so flag the interlock as unlikely.
 2015-01-05 22:12:34 -05:00
Tyler Stachecki
bc77b5f608 Prevent a if statement over ternary expressions. 2015-01-05 22:12:23 -05:00
Tyler Stachecki
d39737a039 Make interrupt exception checks more efficient. 2015-01-05 22:12:13 -05:00
Tyler Stachecki
999ff27b9e Fix a last-minute bug in TLB exceptions. 2015-01-05 22:12:04 -05:00
Tyler Stachecki
134eb07fef Add support for TLB modification exceptions. 2015-01-05 22:11:50 -05:00
Tyler Stachecki
ffebe24c59 Implement cache operations, fix cache op bug. 
If we're doing a cache operation in the DC stage, don't
change the stage of the lines; the cache operations will
do it if needed. Also implement get/set taglo for DC.
 2015-01-04 23:00:42 -05:00
Tyler Stachecki
7ee6eab842 Respect the TLB entry conherency bits. 
If the TLB entry 'C bits' indicate the cache isn't to be
used for that virtual address range... don't use the cache.
 2015-01-04 21:37:13 -05:00
Tyler Stachecki
16daf94430 Move cache functionality to the DC stage. 
This is how the actual processor does it. In addition to
design correctness, we have the added benefit of being able
to support cache instructions whose virtual address lies
in a mapped part of the address space.
 2015-01-04 21:11:22 -05:00
Tyler Stachecki
a648cedc87 More cleanup of the fault/TLB code. 2015-01-04 15:38:56 -05:00