Ronald G. Minnich 72be710b4b With this change, we get all the way to stage 2 and this output, at ... which point we hang: Show all devs... root(Root Device): enabled 1 have_resources 0 initialized 0 cpus: Unknown device path type: 0 cpus(): enabled 1 have_resources 0 initialized 0 apic_0(APIC: 00): enabled 1 have_resources 0 initialized 0 pci_1_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0 pci_0_0(PCI: 00:00.0): enabled 1 have_resources 0 initialized 0 pci_4_0(PCI: 00:04.0): enabled 1 have_resources 0 initialized 0 pci_5_0(PCI: 00:05.0): enabled 1 have_resources 0 initialized 0 pci_18_0(PCI: 00:18.0): enabled 1 have_resources 0 initialized 0 ioport_2e(IOPORT: 2e): enabled 1 have_resources 0 initialized 0 domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0 Phase 6: Initializing devices... Phase 6: Root Device init. Phase 6: PCI: 00:04.0 init. The dts is quite incomplete and that is part of the problem. Doubtless there are other problems :-) But training is indeed working in simnow, and memory is working, and we can return from disable_car as on the geode. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@855 f3766cd6-281f-0410-b1cd-43a5c92072e9		2008-09-02 15:25:06 +00:00
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amd	With this change, we get all the way to stage 2 and this output, at	2008-09-02 15:25:06 +00:00
geodelx	stage1_main() calling conventions changed to use two parameters instead	2008-08-28 02:55:14 +00:00
archelfboot.c	Move include/console/console.h to include/console.h in order to	2007-05-05 20:18:28 +00:00
archtables.c	This set of changes creates irq tables for alix1c and adds the functions	2008-02-09 16:32:59 +00:00
coreboot_table.c	mainboard_vendor and mainboard_name are constant. Follow that convention	2008-08-25 23:54:50 +00:00
i8259.c	Now version 3: LinuxBIOS -> coreboot rename.	2008-01-27 18:54:57 +00:00
isa-dma.c	Ron's arch code., slightly changed. Another one will follow	2007-06-27 21:01:01 +00:00
Kconfig	This gets us back to a compiling k8 target.	2008-08-30 03:35:40 +00:00
keyboard.c	The current parameter situation of post_code() is rather mixed between	2008-01-07 16:34:34 +00:00
ldscript.ld	For Ron: make BOOTBLOCK_SIZE a variable in the ldscript.	2008-08-24 11:31:19 +00:00
Makefile	Enable compilation with -fwhole-program for initram. The setting can be	2008-08-27 01:10:27 +00:00
mc146818rtc.c	We're getting closer. It has been pointed out that this code is not pretty. I agree. Get	2008-08-03 22:42:01 +00:00
pci_ops_auto.c	Here we start to see the good design of 3. In v2, there were pci ops in	2008-08-13 02:41:29 +00:00
pci_ops_conf1.c	Fix a really stupid error on my part :-)	2008-08-30 05:01:43 +00:00
pci_ops_mmconf.c	Constify structs which can be const.	2007-11-26 13:28:52 +00:00
pirq_routing.c	Minor cosmetic and/or license header fixes (trivial).	2008-08-11 21:01:54 +00:00
post_code.c	Now version 3: LinuxBIOS -> coreboot rename.	2008-01-27 18:54:57 +00:00
resourcemap.c	The change to Kconfig is self-acked.	2008-08-13 02:44:46 +00:00
serial.c	Now version 3: LinuxBIOS -> coreboot rename.	2008-01-27 18:54:57 +00:00
speaker.c	Remove superfluous checks for boolean CONFIG_* variables where we tested	2008-02-14 22:34:40 +00:00
stage0_i586.S	stage1_main() calling conventions changed to use two parameters instead	2008-08-28 02:55:14 +00:00
stage1.c	BIST handling. Unless I'm mistaken, we already die() in stage1_main() if	2008-08-28 01:57:14 +00:00
stage1_mtrr.c	One typo and one change to get our bootblock back into 20k.	2008-08-30 03:42:01 +00:00
udelay_io.c	Now version 3: LinuxBIOS -> coreboot rename.	2008-01-27 18:54:57 +00:00